hif.c (9a64e8e0ace51b309fdcff4b4754b3649250382a) hif.c (84caf8005b09e0a4a57fce44119489d1b0bbbe94)
1/*
2 * Copyright (c) 2007-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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131 */
132 ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS,
133 (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC);
134 if (ret)
135 ath6kl_warn("Failed to clear debug interrupt: %d\n", ret);
136
137 ath6kl_hif_dump_fw_crash(dev->ar);
138 ath6kl_read_fwlogs(dev->ar);
1/*
2 * Copyright (c) 2007-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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131 */
132 ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS,
133 (u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC);
134 if (ret)
135 ath6kl_warn("Failed to clear debug interrupt: %d\n", ret);
136
137 ath6kl_hif_dump_fw_crash(dev->ar);
138 ath6kl_read_fwlogs(dev->ar);
139 ath6kl_recovery_err_notify(dev->ar, ATH6KL_FW_ASSERT);
139
140 return ret;
141}
142
143/* mailbox recv message polling */
144int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
145 int timeout)
146{

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141 return ret;
142}
143
144/* mailbox recv message polling */
145int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
146 int timeout)
147{

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