| reg.h (87e8b821ed8db3dab03d96cd542e29666bf210aa) | reg.h (2111ac0d888767999c7dd6d1309dcc1fb8012022) |
|---|---|
| 1/* 2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. --- 198 unchanged lines hidden (view full) --- 207 * Only found in 5211 (?) 208 */ 209#define AR5K_RXJLA 0x0038 210 211/* 212 * MIB control register 213 */ 214#define AR5K_MIBC 0x0040 /* Register Address */ | 1/* 2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. --- 198 unchanged lines hidden (view full) --- 207 * Only found in 5211 (?) 208 */ 209#define AR5K_RXJLA 0x0038 210 211/* 212 * MIB control register 213 */ 214#define AR5K_MIBC 0x0040 /* Register Address */ |
| 215#define AR5K_MIBC_COW 0x00000001 /* Warn test indicator */ | 215#define AR5K_MIBC_COW 0x00000001 /* Counter Overflow Warning */ |
| 216#define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */ | 216#define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */ |
| 217#define AR5K_MIBC_CMC 0x00000004 /* Clean MIB Counters */ 218#define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe */ | 217#define AR5K_MIBC_CMC 0x00000004 /* Clear MIB Counters */ 218#define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */ |
| 219 220/* 221 * Timeout prescale register 222 */ 223#define AR5K_TOPS 0x0044 224#define AR5K_TOPS_M 0x0000ffff 225 226/* --- 1284 unchanged lines hidden (view full) --- 1511 * NAV register (current) 1512 */ 1513#define AR5K_NAV_5210 0x808c 1514#define AR5K_NAV_5211 0x8084 1515#define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ 1516 AR5K_NAV_5210 : AR5K_NAV_5211) 1517 1518/* | 219 220/* 221 * Timeout prescale register 222 */ 223#define AR5K_TOPS 0x0044 224#define AR5K_TOPS_M 0x0000ffff 225 226/* --- 1284 unchanged lines hidden (view full) --- 1511 * NAV register (current) 1512 */ 1513#define AR5K_NAV_5210 0x808c 1514#define AR5K_NAV_5211 0x8084 1515#define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ 1516 AR5K_NAV_5210 : AR5K_NAV_5211) 1517 1518/* |
| 1519 * RTS success register | 1519 * MIB counters: 1520 * 1521 * max value is 0xc000, if this is reached we get a MIB interrupt. 1522 * they can be controlled via AR5K_MIBC and are cleared on read. |
| 1520 */ | 1523 */ |
| 1524 1525/* 1526 * RTS success (MIB counter) 1527 */ |
|
| 1521#define AR5K_RTS_OK_5210 0x8090 1522#define AR5K_RTS_OK_5211 0x8088 1523#define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ 1524 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) 1525 1526/* | 1528#define AR5K_RTS_OK_5210 0x8090 1529#define AR5K_RTS_OK_5211 0x8088 1530#define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ 1531 AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) 1532 1533/* |
| 1527 * RTS failure register | 1534 * RTS failure (MIB counter) |
| 1528 */ 1529#define AR5K_RTS_FAIL_5210 0x8094 1530#define AR5K_RTS_FAIL_5211 0x808c 1531#define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1532 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) 1533 1534/* | 1535 */ 1536#define AR5K_RTS_FAIL_5210 0x8094 1537#define AR5K_RTS_FAIL_5211 0x808c 1538#define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1539 AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) 1540 1541/* |
| 1535 * ACK failure register | 1542 * ACK failure (MIB counter) |
| 1536 */ 1537#define AR5K_ACK_FAIL_5210 0x8098 1538#define AR5K_ACK_FAIL_5211 0x8090 1539#define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1540 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) 1541 1542/* | 1543 */ 1544#define AR5K_ACK_FAIL_5210 0x8098 1545#define AR5K_ACK_FAIL_5211 0x8090 1546#define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1547 AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) 1548 1549/* |
| 1543 * FCS failure register | 1550 * FCS failure (MIB counter) |
| 1544 */ 1545#define AR5K_FCS_FAIL_5210 0x809c 1546#define AR5K_FCS_FAIL_5211 0x8094 1547#define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1548 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) 1549 1550/* 1551 * Beacon count register --- 110 unchanged lines hidden (view full) --- 1662#define AR5K_TXPC_CTS_S 8 1663#define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */ 1664#define AR5K_TXPC_CHIRP_S 16 1665#define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */ 1666#define AR5K_TXPC_DOPPLER_S 24 1667 1668/* 1669 * Profile count registers | 1551 */ 1552#define AR5K_FCS_FAIL_5210 0x809c 1553#define AR5K_FCS_FAIL_5211 0x8094 1554#define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ 1555 AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) 1556 1557/* 1558 * Beacon count register --- 110 unchanged lines hidden (view full) --- 1669#define AR5K_TXPC_CTS_S 8 1670#define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */ 1671#define AR5K_TXPC_CHIRP_S 16 1672#define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */ 1673#define AR5K_TXPC_DOPPLER_S 24 1674 1675/* 1676 * Profile count registers |
| 1677 * 1678 * These registers can be cleared and freezed with ATH5K_MIBC, but they do not 1679 * generate a MIB interrupt. 1680 * Instead of overflowing, they shift by one bit to the right. All registers 1681 * shift together, i.e. when one reaches the max, all shift at the same time by 1682 * one bit to the right. This way we should always get consistent values. |
|
| 1670 */ 1671#define AR5K_PROFCNT_TX 0x80ec /* Tx count */ 1672#define AR5K_PROFCNT_RX 0x80f0 /* Rx count */ | 1683 */ 1684#define AR5K_PROFCNT_TX 0x80ec /* Tx count */ 1685#define AR5K_PROFCNT_RX 0x80f0 /* Rx count */ |
| 1673#define AR5K_PROFCNT_RXCLR 0x80f4 /* Clear Rx count */ 1674#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */ | 1686#define AR5K_PROFCNT_RXCLR 0x80f4 /* Busy count */ 1687#define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle counter */ |
| 1675 1676/* 1677 * Quiet period control registers 1678 */ 1679#define AR5K_QUIET_CTL1 0x80fc /* Register Address */ 1680#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */ 1681#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 1682#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */ --- 70 unchanged lines hidden (view full) --- 1753#define AR5K_OFDM_FIL_CNT 0x8124 1754 1755/* 1756 * CCK Filter counter 1757 */ 1758#define AR5K_CCK_FIL_CNT 0x8128 1759 1760/* | 1688 1689/* 1690 * Quiet period control registers 1691 */ 1692#define AR5K_QUIET_CTL1 0x80fc /* Register Address */ 1693#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */ 1694#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 1695#define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */ --- 70 unchanged lines hidden (view full) --- 1766#define AR5K_OFDM_FIL_CNT 0x8124 1767 1768/* 1769 * CCK Filter counter 1770 */ 1771#define AR5K_CCK_FIL_CNT 0x8128 1772 1773/* |
| 1761 * PHY Error Counters (?) | 1774 * PHY Error Counters (same masks as AR5K_PHY_ERR_FIL) |
| 1762 */ 1763#define AR5K_PHYERR_CNT1 0x812c 1764#define AR5K_PHYERR_CNT1_MASK 0x8130 1765 1766#define AR5K_PHYERR_CNT2 0x8134 1767#define AR5K_PHYERR_CNT2_MASK 0x8138 1768 | 1775 */ 1776#define AR5K_PHYERR_CNT1 0x812c 1777#define AR5K_PHYERR_CNT1_MASK 0x8130 1778 1779#define AR5K_PHYERR_CNT2 0x8134 1780#define AR5K_PHYERR_CNT2_MASK 0x8138 1781 |
| 1782/* if the PHY Error Counters reach this maximum, we get MIB interrupts */ 1783#define ATH5K_PHYERR_CNT_MAX 0x00c00000 1784 |
|
| 1769/* 1770 * TSF Threshold register (?) 1771 */ 1772#define AR5K_TSF_THRES 0x813c 1773 1774/* 1775 * TODO: Wake On Wireless registers 1776 * Range: 0x8147 - 0x818c --- 192 unchanged lines hidden (view full) --- 1969#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */ 1970 1971/* 1972 * PHY settling register 1973 */ 1974#define AR5K_PHY_SETTLING 0x9844 /* Register Address */ 1975#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ 1976#define AR5K_PHY_SETTLING_AGC_S 0 | 1785/* 1786 * TSF Threshold register (?) 1787 */ 1788#define AR5K_TSF_THRES 0x813c 1789 1790/* 1791 * TODO: Wake On Wireless registers 1792 * Range: 0x8147 - 0x818c --- 192 unchanged lines hidden (view full) --- 1985#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */ 1986 1987/* 1988 * PHY settling register 1989 */ 1990#define AR5K_PHY_SETTLING 0x9844 /* Register Address */ 1991#define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ 1992#define AR5K_PHY_SETTLING_AGC_S 0 |
| 1977#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */ | 1993#define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settling time */ |
| 1978#define AR5K_PHY_SETTLING_SWITCH_S 7 1979 1980/* 1981 * PHY Gain registers 1982 */ 1983#define AR5K_PHY_GAIN 0x9848 /* Register Address */ 1984#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */ 1985#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12 --- 196 unchanged lines hidden (view full) --- 2182#define AR5K_PHY_MAX_RX_LEN 0x991c 2183 2184/* 2185 * PHY timing register 4 2186 * I(nphase)/Q(adrature) calibration register [5111+] 2187 */ 2188#define AR5K_PHY_IQ 0x9920 /* Register Address */ 2189#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ | 1994#define AR5K_PHY_SETTLING_SWITCH_S 7 1995 1996/* 1997 * PHY Gain registers 1998 */ 1999#define AR5K_PHY_GAIN 0x9848 /* Register Address */ 2000#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */ 2001#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12 --- 196 unchanged lines hidden (view full) --- 2198#define AR5K_PHY_MAX_RX_LEN 0x991c 2199 2200/* 2201 * PHY timing register 4 2202 * I(nphase)/Q(adrature) calibration register [5111+] 2203 */ 2204#define AR5K_PHY_IQ 0x9920 /* Register Address */ 2205#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ |
| 2190#define AR5K_PHY_IQ_CORR_Q_Q_COFF_S 0 | |
| 2191#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ 2192#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 2193#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ 2194#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */ 2195#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 2196#define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ 2197#define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */ 2198#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */ --- 390 unchanged lines hidden --- | 2206#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ 2207#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 2208#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ 2209#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */ 2210#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 2211#define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ 2212#define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */ 2213#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */ --- 390 unchanged lines hidden --- |