ath5k.h (c9494727cf293ae2ec66af57547a3e79c724fec2) ath5k.h (2111ac0d888767999c7dd6d1309dcc1fb8012022)
1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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197#define AR5K_TUNE_CWMAX 1023
198#define AR5K_TUNE_CWMAX_11B 1023
199#define AR5K_TUNE_CWMAX_XR 7
200#define AR5K_TUNE_NOISE_FLOOR -72
201#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
202#define AR5K_TUNE_MAX_TXPOWER 63
203#define AR5K_TUNE_DEFAULT_TXPOWER 25
204#define AR5K_TUNE_TPC_TXPOWER false
1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *

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197#define AR5K_TUNE_CWMAX 1023
198#define AR5K_TUNE_CWMAX_11B 1023
199#define AR5K_TUNE_CWMAX_XR 7
200#define AR5K_TUNE_NOISE_FLOOR -72
201#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
202#define AR5K_TUNE_MAX_TXPOWER 63
203#define AR5K_TUNE_DEFAULT_TXPOWER 25
204#define AR5K_TUNE_TPC_TXPOWER false
205#define AR5K_TUNE_HWTXTRIES 4
205#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */
206#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
206
207#define AR5K_INIT_CARR_SENSE_EN 1
208
209/*Swap RX/TX Descriptor for big endian archs*/
210#if defined(__BIG_ENDIAN)
211#define AR5K_INIT_CFG ( \
212 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
213)

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609/**************************\
610 BEACON TIMERS DEFINITIONS
611\**************************/
612
613#define AR5K_BEACON_PERIOD 0x0000ffff
614#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
615#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
616
207
208#define AR5K_INIT_CARR_SENSE_EN 1
209
210/*Swap RX/TX Descriptor for big endian archs*/
211#if defined(__BIG_ENDIAN)
212#define AR5K_INIT_CFG ( \
213 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
214)

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610/**************************\
611 BEACON TIMERS DEFINITIONS
612\**************************/
613
614#define AR5K_BEACON_PERIOD 0x0000ffff
615#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
616#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
617
617#if 0
618/**
619 * struct ath5k_beacon_state - Per-station beacon timer state.
620 * @bs_interval: in TU's, can also include the above flags
621 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
622 * Point Coordination Function capable AP
623 */
624struct ath5k_beacon_state {
625 u32 bs_next_beacon;
626 u32 bs_next_dtim;
627 u32 bs_interval;
628 u8 bs_dtim_period;
629 u8 bs_cfp_period;
630 u16 bs_cfp_max_duration;
631 u16 bs_cfp_du_remain;
632 u16 bs_tim_offset;
633 u16 bs_sleep_duration;
634 u16 bs_bmiss_threshold;
635 u32 bs_cfp_next;
636};
637#endif
638
618
639
640/*
641 * TSF to TU conversion:
642 *
643 * TSF is a 64bit value in usec (microseconds).
644 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
645 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
646 */
647#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)

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817 * operation without reseting the card, that's why int_fatal is not
818 * common for all chips.
819 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
820 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
821 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
822 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
823 * We currently do increments on interrupt by
824 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
619/*
620 * TSF to TU conversion:
621 *
622 * TSF is a 64bit value in usec (microseconds).
623 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
624 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
625 */
626#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)

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796 * operation without reseting the card, that's why int_fatal is not
797 * common for all chips.
798 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
799 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
800 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
801 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
802 * We currently do increments on interrupt by
803 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
825 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
826 * checked. We should do this with ath5k_hw_update_mib_counters() but
827 * it seems we should also then do some noise immunity work.
804 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
805 * one of the PHY error counters reached the maximum value and should be
806 * read and cleared.
828 * @AR5K_INT_RXPHY: RX PHY Error
829 * @AR5K_INT_RXKCM: RX Key cache miss
830 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
831 * beacon that must be handled in software. The alternative is if you
832 * have VEOL support, in that case you let the hardware deal with things.
833 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
834 * beacons from the AP have associated with, we should probably try to
835 * reassociate. When in IBSS mode this might mean we have not received

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907 | AR5K_INT_BRSSI
908 | AR5K_INT_BMISS
909 | AR5K_INT_GPIO
910 | AR5K_INT_GLOBAL,
911
912 AR5K_INT_NOCARD = 0xffffffff
913};
914
807 * @AR5K_INT_RXPHY: RX PHY Error
808 * @AR5K_INT_RXKCM: RX Key cache miss
809 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
810 * beacon that must be handled in software. The alternative is if you
811 * have VEOL support, in that case you let the hardware deal with things.
812 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
813 * beacons from the AP have associated with, we should probably try to
814 * reassociate. When in IBSS mode this might mean we have not received

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886 | AR5K_INT_BRSSI
887 | AR5K_INT_BMISS
888 | AR5K_INT_GPIO
889 | AR5K_INT_GLOBAL,
890
891 AR5K_INT_NOCARD = 0xffffffff
892};
893
915/* Software interrupts used for calibration */
916enum ath5k_software_interrupt {
917 AR5K_SWI_FULL_CALIBRATION = 0x01,
918 AR5K_SWI_SHORT_CALIBRATION = 0x02,
894/* mask which calibration is active at the moment */
895enum ath5k_calibration_mask {
896 AR5K_CALIBRATION_FULL = 0x01,
897 AR5K_CALIBRATION_SHORT = 0x02,
898 AR5K_CALIBRATION_ANI = 0x04,
919};
920
921/*
922 * Power management
923 */
924enum ath5k_power_mode {
925 AR5K_PM_UNDEFINED = 0,
926 AR5K_PM_AUTO,

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999 struct ath5k_eeprom_info cap_eeprom;
1000
1001 /*
1002 * Queue information
1003 */
1004 struct {
1005 u8 q_tx_num;
1006 } cap_queues;
899};
900
901/*
902 * Power management
903 */
904enum ath5k_power_mode {
905 AR5K_PM_UNDEFINED = 0,
906 AR5K_PM_AUTO,

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979 struct ath5k_eeprom_info cap_eeprom;
980
981 /*
982 * Queue information
983 */
984 struct {
985 u8 q_tx_num;
986 } cap_queues;
987
988 bool cap_has_phyerr_counters;
1007};
1008
1009/* size of noise floor history (keep it a power of two) */
1010#define ATH5K_NF_CAL_HIST_MAX 8
1011struct ath5k_nfcal_hist
1012{
1013 s16 index; /* current index into nfval */
1014 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1015};
1016
989};
990
991/* size of noise floor history (keep it a power of two) */
992#define ATH5K_NF_CAL_HIST_MAX 8
993struct ath5k_nfcal_hist
994{
995 s16 index; /* current index into nfval */
996 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
997};
998
999/**
1000 * struct avg_val - Helper structure for average calculation
1001 * @avg: contains the actual average value
1002 * @avg_weight: is used internally during calculation to prevent rounding errors
1003 */
1004struct ath5k_avg_val {
1005 int avg;
1006 int avg_weight;
1007};
1017
1018/***************************************\
1019 HARDWARE ABSTRACTION LAYER STRUCTURE
1020\***************************************/
1021
1022/*
1023 * Misc defines
1024 */
1025
1026#define AR5K_MAX_GPIO 10
1027#define AR5K_MAX_RF_BANKS 8
1028
1029/* TODO: Clean up and merge with ath5k_softc */
1030struct ath5k_hw {
1008
1009/***************************************\
1010 HARDWARE ABSTRACTION LAYER STRUCTURE
1011\***************************************/
1012
1013/*
1014 * Misc defines
1015 */
1016
1017#define AR5K_MAX_GPIO 10
1018#define AR5K_MAX_RF_BANKS 8
1019
1020/* TODO: Clean up and merge with ath5k_softc */
1021struct ath5k_hw {
1031 u32 ah_magic;
1032 struct ath_common common;
1033
1034 struct ath5k_softc *ah_sc;
1035 void __iomem *ah_iobase;
1036
1037 enum ath5k_int ah_imr;
1038
1022 struct ath_common common;
1023
1024 struct ath5k_softc *ah_sc;
1025 void __iomem *ah_iobase;
1026
1027 enum ath5k_int ah_imr;
1028
1039 enum nl80211_iftype ah_op_mode;
1040 struct ieee80211_channel *ah_current_channel;
1041 bool ah_turbo;
1042 bool ah_calibration;
1043 bool ah_single_chip;
1044 bool ah_aes_support;
1045 bool ah_combined_mic;
1046
1047 enum ath5k_version ah_version;
1048 enum ath5k_radio ah_radio;
1049 u32 ah_phy;
1050 u32 ah_mac_srev;
1051 u16 ah_mac_version;
1029 struct ieee80211_channel *ah_current_channel;
1030 bool ah_turbo;
1031 bool ah_calibration;
1032 bool ah_single_chip;
1033 bool ah_aes_support;
1034 bool ah_combined_mic;
1035
1036 enum ath5k_version ah_version;
1037 enum ath5k_radio ah_radio;
1038 u32 ah_phy;
1039 u32 ah_mac_srev;
1040 u16 ah_mac_version;
1052 u16 ah_mac_revision;
1053 u16 ah_phy_revision;
1054 u16 ah_radio_5ghz_revision;
1055 u16 ah_radio_2ghz_revision;
1056
1057#define ah_modes ah_capabilities.cap_mode
1058#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1059
1060 u32 ah_atim_window;

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1066
1067 /* Antenna Control */
1068 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1069 u8 ah_ant_mode;
1070 u8 ah_tx_ant;
1071 u8 ah_def_ant;
1072 bool ah_software_retry;
1073
1041 u16 ah_phy_revision;
1042 u16 ah_radio_5ghz_revision;
1043 u16 ah_radio_2ghz_revision;
1044
1045#define ah_modes ah_capabilities.cap_mode
1046#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1047
1048 u32 ah_atim_window;

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1054
1055 /* Antenna Control */
1056 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1057 u8 ah_ant_mode;
1058 u8 ah_tx_ant;
1059 u8 ah_def_ant;
1060 bool ah_software_retry;
1061
1074 int ah_gpio_npins;
1075
1076 struct ath5k_capabilities ah_capabilities;
1077
1078 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1079 u32 ah_txq_status;
1080 u32 ah_txq_imr_txok;
1081 u32 ah_txq_imr_txerr;
1082 u32 ah_txq_imr_txurn;
1083 u32 ah_txq_imr_txdesc;

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1118 struct {
1119 bool r_enabled;
1120 int r_last_alert;
1121 struct ieee80211_channel r_last_channel;
1122 } ah_radar;
1123
1124 struct ath5k_nfcal_hist ah_nfcal_hist;
1125
1062 struct ath5k_capabilities ah_capabilities;
1063
1064 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1065 u32 ah_txq_status;
1066 u32 ah_txq_imr_txok;
1067 u32 ah_txq_imr_txerr;
1068 u32 ah_txq_imr_txurn;
1069 u32 ah_txq_imr_txdesc;

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1104 struct {
1105 bool r_enabled;
1106 int r_last_alert;
1107 struct ieee80211_channel r_last_channel;
1108 } ah_radar;
1109
1110 struct ath5k_nfcal_hist ah_nfcal_hist;
1111
1112 /* average beacon RSSI in our BSS (used by ANI) */
1113 struct ath5k_avg_val ah_beacon_rssi_avg;
1114
1126 /* noise floor from last periodic calibration */
1127 s32 ah_noise_floor;
1128
1129 /* Calibration timestamp */
1115 /* noise floor from last periodic calibration */
1116 s32 ah_noise_floor;
1117
1118 /* Calibration timestamp */
1130 unsigned long ah_cal_tstamp;
1119 unsigned long ah_cal_next_full;
1120 unsigned long ah_cal_next_ani;
1131
1121
1132 /* Calibration interval (secs) */
1133 u8 ah_cal_intval;
1122 /* Calibration mask */
1123 u8 ah_cal_mask;
1134
1124
1135 /* Software interrupt mask */
1136 u8 ah_swi_mask;
1137
1138 /*
1139 * Function pointers
1140 */
1141 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1142 u32 size, unsigned int flags);
1143 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1125 /*
1126 * Function pointers
1127 */
1128 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1129 u32 size, unsigned int flags);
1130 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1144 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1131 unsigned int, unsigned int, int, enum ath5k_pkt_type,
1145 unsigned int, unsigned int, unsigned int, unsigned int,
1132 unsigned int, unsigned int, unsigned int, unsigned int,
1146 unsigned int, unsigned int, unsigned int);
1133 unsigned int, unsigned int, unsigned int, unsigned int);
1147 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1148 unsigned int, unsigned int, unsigned int, unsigned int,
1149 unsigned int, unsigned int);
1150 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1151 struct ath5k_tx_status *);
1152 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1153 struct ath5k_rx_status *);
1154};
1155
1156/*
1157 * Prototypes
1158 */
1159
1160/* Attach/Detach Functions */
1134 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1135 unsigned int, unsigned int, unsigned int, unsigned int,
1136 unsigned int, unsigned int);
1137 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1138 struct ath5k_tx_status *);
1139 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1140 struct ath5k_rx_status *);
1141};
1142
1143/*
1144 * Prototypes
1145 */
1146
1147/* Attach/Detach Functions */
1161extern int ath5k_hw_attach(struct ath5k_softc *sc);
1162extern void ath5k_hw_detach(struct ath5k_hw *ah);
1148int ath5k_hw_attach(struct ath5k_softc *sc);
1149void ath5k_hw_detach(struct ath5k_hw *ah);
1163
1164/* LED functions */
1150
1151/* LED functions */
1165extern int ath5k_init_leds(struct ath5k_softc *sc);
1166extern void ath5k_led_enable(struct ath5k_softc *sc);
1167extern void ath5k_led_off(struct ath5k_softc *sc);
1168extern void ath5k_unregister_leds(struct ath5k_softc *sc);
1152int ath5k_init_leds(struct ath5k_softc *sc);
1153void ath5k_led_enable(struct ath5k_softc *sc);
1154void ath5k_led_off(struct ath5k_softc *sc);
1155void ath5k_unregister_leds(struct ath5k_softc *sc);
1169
1170/* Reset Functions */
1156
1157/* Reset Functions */
1171extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1172extern int ath5k_hw_on_hold(struct ath5k_hw *ah);
1173extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
1158int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1159int ath5k_hw_on_hold(struct ath5k_hw *ah);
1160int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1161 struct ieee80211_channel *channel, bool change_channel);
1162int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1163 bool is_set);
1174/* Power management functions */
1164/* Power management functions */
1175extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
1176
1177/* DMA Related Functions */
1165
1166/* DMA Related Functions */
1178extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1179extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1180extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1181extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1182extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1183extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1184extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1185extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1167void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1168int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1169u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1170void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1171int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1172int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1173u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1174int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1186 u32 phys_addr);
1175 u32 phys_addr);
1187extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1176int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1188/* Interrupt handling */
1177/* Interrupt handling */
1189extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1190extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1191extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1192ath5k_int new_mask);
1193extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
1178bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1179int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1180enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1181void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1194
1195/* EEPROM access functions */
1182
1183/* EEPROM access functions */
1196extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1197extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
1198extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1199extern bool ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
1184int ath5k_eeprom_init(struct ath5k_hw *ah);
1185void ath5k_eeprom_detach(struct ath5k_hw *ah);
1186int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1200
1201/* Protocol Control Unit Functions */
1187
1188/* Protocol Control Unit Functions */
1202extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1203extern void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1189extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1190void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1204/* BSSID Functions */
1191/* BSSID Functions */
1205extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1206extern void ath5k_hw_set_associd(struct ath5k_hw *ah);
1207extern void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1192int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1193void ath5k_hw_set_associd(struct ath5k_hw *ah);
1194void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1208/* Receive start/stop functions */
1195/* Receive start/stop functions */
1209extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1210extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1196void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1197void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1211/* RX Filter functions */
1198/* RX Filter functions */
1212extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1213extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1214extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1215extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1216extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1199void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1200u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1201void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1217/* Beacon control functions */
1202/* Beacon control functions */
1218extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1219extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1220extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1221extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1222extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1223#if 0
1224extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1225extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1226extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1227#endif
1203u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1204void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1205void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1206void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1228/* ACK bit rate */
1229void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1207/* ACK bit rate */
1208void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1230/* ACK/CTS Timeouts */
1231extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1232extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1233extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1234extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1235/* Clock rate related functions */
1236unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1237unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1238unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah);
1239/* Key table (WEP) functions */
1209/* Clock rate related functions */
1210unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1211unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1212unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah);
1213/* Key table (WEP) functions */
1240extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1241extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1242extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1243extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1214int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1215int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
1216 const struct ieee80211_key_conf *key, const u8 *mac);
1217int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1244
1245/* Queue Control Unit, DFS Control Unit Functions */
1218
1219/* Queue Control Unit, DFS Control Unit Functions */
1246extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
1247extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1248 const struct ath5k_txq_info *queue_info);
1249extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1250 enum ath5k_tx_queue queue_type,
1251 struct ath5k_txq_info *queue_info);
1252extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1253extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1254extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1255extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
1256extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1220int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1221 struct ath5k_txq_info *queue_info);
1222int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1223 const struct ath5k_txq_info *queue_info);
1224int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1225 enum ath5k_tx_queue queue_type,
1226 struct ath5k_txq_info *queue_info);
1227u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1228void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1229int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1230int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1257
1258/* Hardware Descriptor Functions */
1231
1232/* Hardware Descriptor Functions */
1259extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1233int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1260
1261/* GPIO Functions */
1234
1235/* GPIO Functions */
1262extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1263extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1264extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1265extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1266extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1267extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1236void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1237int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1238int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1239u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1240int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1241void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1242 u32 interrupt_level);
1268
1269/* rfkill Functions */
1243
1244/* rfkill Functions */
1270extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1271extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1245void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1246void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1272
1273/* Misc functions */
1274int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1247
1248/* Misc functions */
1249int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1275extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1276extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1277extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1250int ath5k_hw_get_capability(struct ath5k_hw *ah,
1251 enum ath5k_capability_type cap_type, u32 capability,
1252 u32 *result);
1253int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1254int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1278
1279/* Initial register settings functions */
1255
1256/* Initial register settings functions */
1280extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1257int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1281
1282/* Initialize RF */
1258
1259/* Initialize RF */
1283extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1284 struct ieee80211_channel *channel,
1285 unsigned int mode);
1286extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1287extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1288extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1260int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1261 struct ieee80211_channel *channel,
1262 unsigned int mode);
1263int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1264enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1265int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1289/* PHY/RF channel functions */
1266/* PHY/RF channel functions */
1290extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1291extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1267bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1268int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1292/* PHY calibration */
1293void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1269/* PHY calibration */
1270void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1294extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1295extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1296extern s16 ath5k_hw_get_noise_floor(struct ath5k_hw *ah);
1297extern void ath5k_hw_calibration_poll(struct ath5k_hw *ah);
1271int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1272 struct ieee80211_channel *channel);
1298/* Spur mitigation */
1299bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1273/* Spur mitigation */
1274bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1300 struct ieee80211_channel *channel);
1275 struct ieee80211_channel *channel);
1301void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1276void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1302 struct ieee80211_channel *channel);
1277 struct ieee80211_channel *channel);
1303/* Misc PHY functions */
1278/* Misc PHY functions */
1304extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1305extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1279u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1280int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1306/* Antenna control */
1281/* Antenna control */
1307extern void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1308extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant);
1309extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1282void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1310/* TX power setup */
1283/* TX power setup */
1311extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, u8 ee_mode, u8 txpower);
1312extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1284int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1285 u8 ee_mode, u8 txpower);
1286int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1313
1314/*
1315 * Functions used internaly
1316 */
1317
1318static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1319{
1320 return &ah->common;

--- 9 unchanged lines hidden (view full) ---

1330 return ioread32(ah->ah_iobase + reg);
1331}
1332
1333static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1334{
1335 iowrite32(val, ah->ah_iobase + reg);
1336}
1337
1287
1288/*
1289 * Functions used internaly
1290 */
1291
1292static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1293{
1294 return &ah->common;

--- 9 unchanged lines hidden (view full) ---

1304 return ioread32(ah->ah_iobase + reg);
1305}
1306
1307static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1308{
1309 iowrite32(val, ah->ah_iobase + reg);
1310}
1311
1338#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1339/*
1340 * Check if a register write has been completed
1341 */
1342static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1343 u32 val, bool is_set)
1344{
1345 int i;
1346 u32 data;
1347
1348 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1349 data = ath5k_hw_reg_read(ah, reg);
1350 if (is_set && (data & flag))
1351 break;
1352 else if ((data & flag) == val)
1353 break;
1354 udelay(15);
1355 }
1356
1357 return (i <= 0) ? -EAGAIN : 0;
1358}
1359#endif
1360
1361static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1362{
1363 u32 retval = 0, bit, i;
1364
1365 for (i = 0; i < bits; i++) {
1366 bit = (val >> i) & 1;
1367 retval = (retval << 1) | bit;
1368 }
1369
1370 return retval;
1371}
1372
1312static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1313{
1314 u32 retval = 0, bit, i;
1315
1316 for (i = 0; i < bits; i++) {
1317 bit = (val >> i) & 1;
1318 retval = (retval << 1) | bit;
1319 }
1320
1321 return retval;
1322}
1323
1373static inline int ath5k_pad_size(int hdrlen)
1324#define AVG_SAMPLES 8
1325#define AVG_FACTOR 1000
1326
1327/**
1328 * ath5k_moving_average - Exponentially weighted moving average
1329 * @avg: average structure
1330 * @val: current value
1331 *
1332 * This implementation make use of a struct ath5k_avg_val to prevent rounding
1333 * errors.
1334 */
1335static inline struct ath5k_avg_val
1336ath5k_moving_average(const struct ath5k_avg_val avg, const int val)
1374{
1337{
1375 return (hdrlen < 24) ? 0 : hdrlen & 3;
1338 struct ath5k_avg_val new;
1339 new.avg_weight = avg.avg_weight ?
1340 (((avg.avg_weight * ((AVG_SAMPLES) - 1)) +
1341 (val * (AVG_FACTOR))) / (AVG_SAMPLES)) :
1342 (val * (AVG_FACTOR));
1343 new.avg = new.avg_weight / (AVG_FACTOR);
1344 return new;
1376}
1377
1378#endif
1345}
1346
1347#endif