vmxnet3_drv.c (c84d6efd363a3948eb32ec40d46bab6338580454) vmxnet3_drv.c (8e95a2026f3b43f7c3d676adaccd2de9532e8dcc)
1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.

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19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.

--- 10 unchanged lines hidden (view full) ---

19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
27#include <net/ip6_checksum.h>
28
27#include "vmxnet3_int.h"
28
29char vmxnet3_driver_name[] = "vmxnet3";
30#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
31
29#include "vmxnet3_int.h"
30
31char vmxnet3_driver_name[] = "vmxnet3";
32#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
33
32
33/*
34 * PCI Device ID Table
35 * Last entry must be all 0s
36 */
37static const struct pci_device_id vmxnet3_pciid_table[] = {
38 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
39 {0}
40};

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146 adapter->netdev->name);
147 if (netif_carrier_ok(adapter->netdev))
148 netif_carrier_off(adapter->netdev);
149
150 vmxnet3_tq_stop(&adapter->tx_queue, adapter);
151 }
152}
153
34/*
35 * PCI Device ID Table
36 * Last entry must be all 0s
37 */
38static const struct pci_device_id vmxnet3_pciid_table[] = {
39 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
40 {0}
41};

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147 adapter->netdev->name);
148 if (netif_carrier_ok(adapter->netdev))
149 netif_carrier_off(adapter->netdev);
150
151 vmxnet3_tq_stop(&adapter->tx_queue, adapter);
152 }
153}
154
154
155static void
156vmxnet3_process_events(struct vmxnet3_adapter *adapter)
157{
155static void
156vmxnet3_process_events(struct vmxnet3_adapter *adapter)
157{
158 u32 events = adapter->shared->ecr;
158 u32 events = le32_to_cpu(adapter->shared->ecr);
159 if (!events)
160 return;
161
162 vmxnet3_ack_events(adapter, events);
163
164 /* Check if link state has changed */
165 if (events & VMXNET3_ECR_LINK)
166 vmxnet3_check_link(adapter);
167
168 /* Check if there is an error on xmit/recv queues */
169 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
170 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
171 VMXNET3_CMD_GET_QUEUE_STATUS);
172
173 if (adapter->tqd_start->status.stopped) {
174 printk(KERN_ERR "%s: tq error 0x%x\n",
175 adapter->netdev->name,
159 if (!events)
160 return;
161
162 vmxnet3_ack_events(adapter, events);
163
164 /* Check if link state has changed */
165 if (events & VMXNET3_ECR_LINK)
166 vmxnet3_check_link(adapter);
167
168 /* Check if there is an error on xmit/recv queues */
169 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
170 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
171 VMXNET3_CMD_GET_QUEUE_STATUS);
172
173 if (adapter->tqd_start->status.stopped) {
174 printk(KERN_ERR "%s: tq error 0x%x\n",
175 adapter->netdev->name,
176 adapter->tqd_start->status.error);
176 le32_to_cpu(adapter->tqd_start->status.error));
177 }
178 if (adapter->rqd_start->status.stopped) {
179 printk(KERN_ERR "%s: rq error 0x%x\n",
180 adapter->netdev->name,
181 adapter->rqd_start->status.error);
182 }
183
184 schedule_work(&adapter->work);
185 }
186}
187
177 }
178 if (adapter->rqd_start->status.stopped) {
179 printk(KERN_ERR "%s: rq error 0x%x\n",
180 adapter->netdev->name,
181 adapter->rqd_start->status.error);
182 }
183
184 schedule_work(&adapter->work);
185 }
186}
187
188#ifdef __BIG_ENDIAN_BITFIELD
189/*
190 * The device expects the bitfields in shared structures to be written in
191 * little endian. When CPU is big endian, the following routines are used to
192 * correctly read and write into ABI.
193 * The general technique used here is : double word bitfields are defined in
194 * opposite order for big endian architecture. Then before reading them in
195 * driver the complete double word is translated using le32_to_cpu. Similarly
196 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
197 * double words into required format.
198 * In order to avoid touching bits in shared structure more than once, temporary
199 * descriptors are used. These are passed as srcDesc to following functions.
200 */
201static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
202 struct Vmxnet3_RxDesc *dstDesc)
203{
204 u32 *src = (u32 *)srcDesc + 2;
205 u32 *dst = (u32 *)dstDesc + 2;
206 dstDesc->addr = le64_to_cpu(srcDesc->addr);
207 *dst = le32_to_cpu(*src);
208 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
209}
188
210
211static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
212 struct Vmxnet3_TxDesc *dstDesc)
213{
214 int i;
215 u32 *src = (u32 *)(srcDesc + 1);
216 u32 *dst = (u32 *)(dstDesc + 1);
217
218 /* Working backwards so that the gen bit is set at the end. */
219 for (i = 2; i > 0; i--) {
220 src--;
221 dst--;
222 *dst = cpu_to_le32(*src);
223 }
224}
225
226
227static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
228 struct Vmxnet3_RxCompDesc *dstDesc)
229{
230 int i = 0;
231 u32 *src = (u32 *)srcDesc;
232 u32 *dst = (u32 *)dstDesc;
233 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
234 *dst = le32_to_cpu(*src);
235 src++;
236 dst++;
237 }
238}
239
240
241/* Used to read bitfield values from double words. */
242static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
243{
244 u32 temp = le32_to_cpu(*bitfield);
245 u32 mask = ((1 << size) - 1) << pos;
246 temp &= mask;
247 temp >>= pos;
248 return temp;
249}
250
251
252
253#endif /* __BIG_ENDIAN_BITFIELD */
254
255#ifdef __BIG_ENDIAN_BITFIELD
256
257# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
258 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
259 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
260# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
261 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
262 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
263# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
264 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
265 VMXNET3_TCD_GEN_SIZE)
266# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
267 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
268# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
269 (dstrcd) = (tmp); \
270 vmxnet3_RxCompToCPU((rcd), (tmp)); \
271 } while (0)
272# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
273 (dstrxd) = (tmp); \
274 vmxnet3_RxDescToCPU((rxd), (tmp)); \
275 } while (0)
276
277#else
278
279# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
280# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
281# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
282# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
283# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
284# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
285
286#endif /* __BIG_ENDIAN_BITFIELD */
287
288
189static void
190vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
191 struct pci_dev *pdev)
192{
193 if (tbi->map_type == VMXNET3_MAP_SINGLE)
194 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
195 PCI_DMA_TODEVICE);
196 else if (tbi->map_type == VMXNET3_MAP_PAGE)

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207vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
208 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
209{
210 struct sk_buff *skb;
211 int entries = 0;
212
213 /* no out of order completion */
214 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
289static void
290vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
291 struct pci_dev *pdev)
292{
293 if (tbi->map_type == VMXNET3_MAP_SINGLE)
294 pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
295 PCI_DMA_TODEVICE);
296 else if (tbi->map_type == VMXNET3_MAP_PAGE)

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307vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
308 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
309{
310 struct sk_buff *skb;
311 int entries = 0;
312
313 /* no out of order completion */
314 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
215 BUG_ON(tq->tx_ring.base[eop_idx].txd.eop != 1);
315 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
216
217 skb = tq->buf_info[eop_idx].skb;
218 BUG_ON(skb == NULL);
219 tq->buf_info[eop_idx].skb = NULL;
220
221 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
222
223 while (tq->tx_ring.next2comp != eop_idx) {

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241static int
242vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
243 struct vmxnet3_adapter *adapter)
244{
245 int completed = 0;
246 union Vmxnet3_GenericDesc *gdesc;
247
248 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
316
317 skb = tq->buf_info[eop_idx].skb;
318 BUG_ON(skb == NULL);
319 tq->buf_info[eop_idx].skb = NULL;
320
321 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
322
323 while (tq->tx_ring.next2comp != eop_idx) {

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341static int
342vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
343 struct vmxnet3_adapter *adapter)
344{
345 int completed = 0;
346 union Vmxnet3_GenericDesc *gdesc;
347
348 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
249 while (gdesc->tcd.gen == tq->comp_ring.gen) {
250 completed += vmxnet3_unmap_pkt(gdesc->tcd.txdIdx, tq,
251 adapter->pdev, adapter);
349 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
350 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
351 &gdesc->tcd), tq, adapter->pdev,
352 adapter);
252
253 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
254 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
255 }
256
257 if (completed) {
258 spin_lock(&tq->tx_lock);
259 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&

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467 PCI_DMA_FROMDEVICE);
468 } else {
469 /* rx buffers skipped by the device */
470 }
471 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
472 }
473
474 BUG_ON(rbi->dma_addr == 0);
353
354 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
355 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
356 }
357
358 if (completed) {
359 spin_lock(&tq->tx_lock);
360 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&

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568 PCI_DMA_FROMDEVICE);
569 } else {
570 /* rx buffers skipped by the device */
571 }
572 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
573 }
574
575 BUG_ON(rbi->dma_addr == 0);
475 gd->rxd.addr = rbi->dma_addr;
476 gd->dword[2] = (ring->gen << VMXNET3_RXD_GEN_SHIFT) | val |
477 rbi->len;
576 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
577 gd->dword[2] = cpu_to_le32((ring->gen << VMXNET3_RXD_GEN_SHIFT)
578 | val | rbi->len);
478
479 num_allocated++;
480 vmxnet3_cmd_ring_adv_next2fill(ring);
481 }
482 rq->uncommitted[ring_idx] += num_allocated;
483
484 dev_dbg(&adapter->netdev->dev,
485 "alloc_rx_buf: %d allocated, next2fill %u, next2comp "

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526 /* use the previous gen bit for the SOP desc */
527 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
528
529 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
530 gdesc = ctx->sop_txd; /* both loops below can be skipped */
531
532 /* no need to map the buffer if headers are copied */
533 if (ctx->copy_size) {
579
580 num_allocated++;
581 vmxnet3_cmd_ring_adv_next2fill(ring);
582 }
583 rq->uncommitted[ring_idx] += num_allocated;
584
585 dev_dbg(&adapter->netdev->dev,
586 "alloc_rx_buf: %d allocated, next2fill %u, next2comp "

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627 /* use the previous gen bit for the SOP desc */
628 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
629
630 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
631 gdesc = ctx->sop_txd; /* both loops below can be skipped */
632
633 /* no need to map the buffer if headers are copied */
634 if (ctx->copy_size) {
534 ctx->sop_txd->txd.addr = tq->data_ring.basePA +
635 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
535 tq->tx_ring.next2fill *
636 tq->tx_ring.next2fill *
536 sizeof(struct Vmxnet3_TxDataDesc);
537 ctx->sop_txd->dword[2] = dw2 | ctx->copy_size;
637 sizeof(struct Vmxnet3_TxDataDesc));
638 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
538 ctx->sop_txd->dword[3] = 0;
539
540 tbi = tq->buf_info + tq->tx_ring.next2fill;
541 tbi->map_type = VMXNET3_MAP_NONE;
542
543 dev_dbg(&adapter->netdev->dev,
544 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
639 ctx->sop_txd->dword[3] = 0;
640
641 tbi = tq->buf_info + tq->tx_ring.next2fill;
642 tbi->map_type = VMXNET3_MAP_NONE;
643
644 dev_dbg(&adapter->netdev->dev,
645 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
545 tq->tx_ring.next2fill, ctx->sop_txd->txd.addr,
646 tq->tx_ring.next2fill,
647 le64_to_cpu(ctx->sop_txd->txd.addr),
546 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
547 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
548
549 /* use the right gen for non-SOP desc */
550 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
551 }
552
553 /* linear part can use multiple tx desc if it's big */

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565 skb->data + buf_offset, buf_size,
566 PCI_DMA_TODEVICE);
567
568 tbi->len = buf_size; /* this automatically convert 2^14 to 0 */
569
570 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
571 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
572
648 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
649 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
650
651 /* use the right gen for non-SOP desc */
652 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
653 }
654
655 /* linear part can use multiple tx desc if it's big */

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667 skb->data + buf_offset, buf_size,
668 PCI_DMA_TODEVICE);
669
670 tbi->len = buf_size; /* this automatically convert 2^14 to 0 */
671
672 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
673 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
674
573 gdesc->txd.addr = tbi->dma_addr;
574 gdesc->dword[2] = dw2 | buf_size;
675 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
676 gdesc->dword[2] = cpu_to_le32(dw2 | buf_size);
575 gdesc->dword[3] = 0;
576
577 dev_dbg(&adapter->netdev->dev,
578 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
677 gdesc->dword[3] = 0;
678
679 dev_dbg(&adapter->netdev->dev,
680 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
579 tq->tx_ring.next2fill, gdesc->txd.addr,
580 gdesc->dword[2], gdesc->dword[3]);
681 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
682 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
581 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
582 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
583
584 len -= buf_size;
585 buf_offset += buf_size;
586 }
587
588 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

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594 frag->page_offset, frag->size,
595 PCI_DMA_TODEVICE);
596
597 tbi->len = frag->size;
598
599 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
600 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
601
683 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
684 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
685
686 len -= buf_size;
687 buf_offset += buf_size;
688 }
689
690 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {

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696 frag->page_offset, frag->size,
697 PCI_DMA_TODEVICE);
698
699 tbi->len = frag->size;
700
701 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
702 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
703
602 gdesc->txd.addr = tbi->dma_addr;
603 gdesc->dword[2] = dw2 | frag->size;
704 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
705 gdesc->dword[2] = cpu_to_le32(dw2 | frag->size);
604 gdesc->dword[3] = 0;
605
606 dev_dbg(&adapter->netdev->dev,
607 "txd[%u]: 0x%llu %u %u\n",
706 gdesc->dword[3] = 0;
707
708 dev_dbg(&adapter->netdev->dev,
709 "txd[%u]: 0x%llu %u %u\n",
608 tq->tx_ring.next2fill, gdesc->txd.addr,
609 gdesc->dword[2], gdesc->dword[3]);
710 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
711 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
610 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
611 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
612 }
613
614 ctx->eop_txd = gdesc;
615
616 /* set the last buf_info for the pkt */
617 tbi->skb = skb;

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746vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
747 struct vmxnet3_adapter *adapter, struct net_device *netdev)
748{
749 int ret;
750 u32 count;
751 unsigned long flags;
752 struct vmxnet3_tx_ctx ctx;
753 union Vmxnet3_GenericDesc *gdesc;
712 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
713 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
714 }
715
716 ctx->eop_txd = gdesc;
717
718 /* set the last buf_info for the pkt */
719 tbi->skb = skb;

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848vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
849 struct vmxnet3_adapter *adapter, struct net_device *netdev)
850{
851 int ret;
852 u32 count;
853 unsigned long flags;
854 struct vmxnet3_tx_ctx ctx;
855 union Vmxnet3_GenericDesc *gdesc;
856#ifdef __BIG_ENDIAN_BITFIELD
857 /* Use temporary descriptor to avoid touching bits multiple times */
858 union Vmxnet3_GenericDesc tempTxDesc;
859#endif
754
755 /* conservatively estimate # of descriptors to use */
756 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
757 skb_shinfo(skb)->nr_frags + 1;
758
759 ctx.ipv4 = (skb->protocol == __constant_ntohs(ETH_P_IP));
760
761 ctx.mss = skb_shinfo(skb)->gso_size;

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822 spin_unlock_irqrestore(&tq->tx_lock, flags);
823 return NETDEV_TX_BUSY;
824 }
825
826 /* fill tx descs related to addr & len */
827 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
828
829 /* setup the EOP desc */
860
861 /* conservatively estimate # of descriptors to use */
862 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
863 skb_shinfo(skb)->nr_frags + 1;
864
865 ctx.ipv4 = (skb->protocol == __constant_ntohs(ETH_P_IP));
866
867 ctx.mss = skb_shinfo(skb)->gso_size;

--- 60 unchanged lines hidden (view full) ---

928 spin_unlock_irqrestore(&tq->tx_lock, flags);
929 return NETDEV_TX_BUSY;
930 }
931
932 /* fill tx descs related to addr & len */
933 vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
934
935 /* setup the EOP desc */
830 ctx.eop_txd->dword[3] = VMXNET3_TXD_CQ | VMXNET3_TXD_EOP;
936 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
831
832 /* setup the SOP desc */
937
938 /* setup the SOP desc */
939#ifdef __BIG_ENDIAN_BITFIELD
940 gdesc = &tempTxDesc;
941 gdesc->dword[2] = ctx.sop_txd->dword[2];
942 gdesc->dword[3] = ctx.sop_txd->dword[3];
943#else
833 gdesc = ctx.sop_txd;
944 gdesc = ctx.sop_txd;
945#endif
834 if (ctx.mss) {
835 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
836 gdesc->txd.om = VMXNET3_OM_TSO;
837 gdesc->txd.msscof = ctx.mss;
946 if (ctx.mss) {
947 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
948 gdesc->txd.om = VMXNET3_OM_TSO;
949 gdesc->txd.msscof = ctx.mss;
838 tq->shared->txNumDeferred += (skb->len - gdesc->txd.hlen +
839 ctx.mss - 1) / ctx.mss;
950 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
951 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
840 } else {
841 if (skb->ip_summed == CHECKSUM_PARTIAL) {
842 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
843 gdesc->txd.om = VMXNET3_OM_CSUM;
844 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
845 skb->csum_offset;
846 } else {
847 gdesc->txd.om = 0;
848 gdesc->txd.msscof = 0;
849 }
952 } else {
953 if (skb->ip_summed == CHECKSUM_PARTIAL) {
954 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
955 gdesc->txd.om = VMXNET3_OM_CSUM;
956 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
957 skb->csum_offset;
958 } else {
959 gdesc->txd.om = 0;
960 gdesc->txd.msscof = 0;
961 }
850 tq->shared->txNumDeferred++;
962 le32_add_cpu(&tq->shared->txNumDeferred, 1);
851 }
852
853 if (vlan_tx_tag_present(skb)) {
854 gdesc->txd.ti = 1;
855 gdesc->txd.tci = vlan_tx_tag_get(skb);
856 }
857
963 }
964
965 if (vlan_tx_tag_present(skb)) {
966 gdesc->txd.ti = 1;
967 gdesc->txd.tci = vlan_tx_tag_get(skb);
968 }
969
858 wmb();
859
860 /* finally flips the GEN bit of the SOP desc */
861 gdesc->dword[2] ^= VMXNET3_TXD_GEN;
970 /* finally flips the GEN bit of the SOP desc. */
971 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
972 VMXNET3_TXD_GEN);
973#ifdef __BIG_ENDIAN_BITFIELD
974 /* Finished updating in bitfields of Tx Desc, so write them in original
975 * place.
976 */
977 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
978 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
979 gdesc = ctx.sop_txd;
980#endif
862 dev_dbg(&adapter->netdev->dev,
863 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
864 (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
981 dev_dbg(&adapter->netdev->dev,
982 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
983 (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
865 tq->tx_ring.base), gdesc->txd.addr, gdesc->dword[2],
866 gdesc->dword[3]);
984 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
985 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
867
868 spin_unlock_irqrestore(&tq->tx_lock, flags);
869
986
987 spin_unlock_irqrestore(&tq->tx_lock, flags);
988
870 if (tq->shared->txNumDeferred >= tq->shared->txThreshold) {
989 if (le32_to_cpu(tq->shared->txNumDeferred) >=
990 le32_to_cpu(tq->shared->txThreshold)) {
871 tq->shared->txNumDeferred = 0;
872 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_TXPROD,
873 tq->tx_ring.next2fill);
874 }
875 netdev->trans_start = jiffies;
876
877 return NETDEV_TX_OK;
878

--- 5 unchanged lines hidden (view full) ---

884 return NETDEV_TX_OK;
885}
886
887
888static netdev_tx_t
889vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
890{
891 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
991 tq->shared->txNumDeferred = 0;
992 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_TXPROD,
993 tq->tx_ring.next2fill);
994 }
995 netdev->trans_start = jiffies;
996
997 return NETDEV_TX_OK;
998

--- 5 unchanged lines hidden (view full) ---

1004 return NETDEV_TX_OK;
1005}
1006
1007
1008static netdev_tx_t
1009vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1010{
1011 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
892 struct vmxnet3_tx_queue *tq = &adapter->tx_queue;
893
1012
894 return vmxnet3_tq_xmit(skb, tq, adapter, netdev);
1013 return vmxnet3_tq_xmit(skb, &adapter->tx_queue, adapter, netdev);
895}
896
897
898static void
899vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
900 struct sk_buff *skb,
901 union Vmxnet3_GenericDesc *gdesc)
902{
903 if (!gdesc->rcd.cnc && adapter->rxcsum) {
904 /* typical case: TCP/UDP over IP and both csums are correct */
1014}
1015
1016
1017static void
1018vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1019 struct sk_buff *skb,
1020 union Vmxnet3_GenericDesc *gdesc)
1021{
1022 if (!gdesc->rcd.cnc && adapter->rxcsum) {
1023 /* typical case: TCP/UDP over IP and both csums are correct */
905 if ((gdesc->dword[3] & VMXNET3_RCD_CSUM_OK) ==
1024 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
906 VMXNET3_RCD_CSUM_OK) {
907 skb->ip_summed = CHECKSUM_UNNECESSARY;
908 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
909 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
910 BUG_ON(gdesc->rcd.frg);
911 } else {
912 if (gdesc->rcd.csum) {
913 skb->csum = htons(gdesc->rcd.csum);

--- 38 unchanged lines hidden (view full) ---

952static int
953vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
954 struct vmxnet3_adapter *adapter, int quota)
955{
956 static u32 rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2};
957 u32 num_rxd = 0;
958 struct Vmxnet3_RxCompDesc *rcd;
959 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1025 VMXNET3_RCD_CSUM_OK) {
1026 skb->ip_summed = CHECKSUM_UNNECESSARY;
1027 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1028 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1029 BUG_ON(gdesc->rcd.frg);
1030 } else {
1031 if (gdesc->rcd.csum) {
1032 skb->csum = htons(gdesc->rcd.csum);

--- 38 unchanged lines hidden (view full) ---

1071static int
1072vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1073 struct vmxnet3_adapter *adapter, int quota)
1074{
1075 static u32 rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2};
1076 u32 num_rxd = 0;
1077 struct Vmxnet3_RxCompDesc *rcd;
1078 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
960
961 rcd = &rq->comp_ring.base[rq->comp_ring.next2proc].rcd;
1079#ifdef __BIG_ENDIAN_BITFIELD
1080 struct Vmxnet3_RxDesc rxCmdDesc;
1081 struct Vmxnet3_RxCompDesc rxComp;
1082#endif
1083 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1084 &rxComp);
962 while (rcd->gen == rq->comp_ring.gen) {
963 struct vmxnet3_rx_buf_info *rbi;
964 struct sk_buff *skb;
965 int num_to_alloc;
966 struct Vmxnet3_RxDesc *rxd;
967 u32 idx, ring_idx;
968
969 if (num_rxd >= quota) {
970 /* we may stop even before we see the EOP desc of
971 * the current pkt
972 */
973 break;
974 }
975 num_rxd++;
976
977 idx = rcd->rxdIdx;
978 ring_idx = rcd->rqID == rq->qid ? 0 : 1;
1085 while (rcd->gen == rq->comp_ring.gen) {
1086 struct vmxnet3_rx_buf_info *rbi;
1087 struct sk_buff *skb;
1088 int num_to_alloc;
1089 struct Vmxnet3_RxDesc *rxd;
1090 u32 idx, ring_idx;
1091
1092 if (num_rxd >= quota) {
1093 /* we may stop even before we see the EOP desc of
1094 * the current pkt
1095 */
1096 break;
1097 }
1098 num_rxd++;
1099
1100 idx = rcd->rxdIdx;
1101 ring_idx = rcd->rqID == rq->qid ? 0 : 1;
979
980 rxd = &rq->rx_ring[ring_idx].base[idx].rxd;
1102 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1103 &rxCmdDesc);
981 rbi = rq->buf_info[ring_idx] + idx;
982
1104 rbi = rq->buf_info[ring_idx] + idx;
1105
983 BUG_ON(rxd->addr != rbi->dma_addr || rxd->len != rbi->len);
1106 BUG_ON(rxd->addr != rbi->dma_addr ||
1107 rxd->len != rbi->len);
984
985 if (unlikely(rcd->eop && rcd->err)) {
986 vmxnet3_rx_error(rq, rcd, ctx, adapter);
987 goto rcd_done;
988 }
989
990 if (rcd->sop) { /* first buf of the pkt */
991 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||

--- 81 unchanged lines hidden (view full) ---

1073 VMXNET3_WRITE_BAR0_REG(adapter,
1074 rxprod_reg[ring_idx] + rq->qid * 8,
1075 rq->rx_ring[ring_idx].next2fill);
1076 rq->uncommitted[ring_idx] = 0;
1077 }
1078 }
1079
1080 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1108
1109 if (unlikely(rcd->eop && rcd->err)) {
1110 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1111 goto rcd_done;
1112 }
1113
1114 if (rcd->sop) { /* first buf of the pkt */
1115 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||

--- 81 unchanged lines hidden (view full) ---

1197 VMXNET3_WRITE_BAR0_REG(adapter,
1198 rxprod_reg[ring_idx] + rq->qid * 8,
1199 rq->rx_ring[ring_idx].next2fill);
1200 rq->uncommitted[ring_idx] = 0;
1201 }
1202 }
1203
1204 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1081 rcd = &rq->comp_ring.base[rq->comp_ring.next2proc].rcd;
1205 vmxnet3_getRxComp(rcd,
1206 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1082 }
1083
1084 return num_rxd;
1085}
1086
1087
1088static void
1089vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1090 struct vmxnet3_adapter *adapter)
1091{
1092 u32 i, ring_idx;
1093 struct Vmxnet3_RxDesc *rxd;
1094
1095 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1096 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1207 }
1208
1209 return num_rxd;
1210}
1211
1212
1213static void
1214vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1215 struct vmxnet3_adapter *adapter)
1216{
1217 u32 i, ring_idx;
1218 struct Vmxnet3_RxDesc *rxd;
1219
1220 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1221 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1097 rxd = &rq->rx_ring[ring_idx].base[i].rxd;
1222#ifdef __BIG_ENDIAN_BITFIELD
1223 struct Vmxnet3_RxDesc rxDesc;
1224#endif
1225 vmxnet3_getRxDesc(rxd,
1226 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1098
1099 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1100 rq->buf_info[ring_idx][i].skb) {
1101 pci_unmap_single(adapter->pdev, rxd->addr,
1102 rxd->len, PCI_DMA_FROMDEVICE);
1103 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1104 rq->buf_info[ring_idx][i].skb = NULL;
1105 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&

--- 235 unchanged lines hidden (view full) ---

1341 int err;
1342
1343#ifdef CONFIG_PCI_MSI
1344 if (adapter->intr.type == VMXNET3_IT_MSIX) {
1345 /* we only use 1 MSI-X vector */
1346 err = request_irq(adapter->intr.msix_entries[0].vector,
1347 vmxnet3_intr, 0, adapter->netdev->name,
1348 adapter->netdev);
1227
1228 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1229 rq->buf_info[ring_idx][i].skb) {
1230 pci_unmap_single(adapter->pdev, rxd->addr,
1231 rxd->len, PCI_DMA_FROMDEVICE);
1232 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1233 rq->buf_info[ring_idx][i].skb = NULL;
1234 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&

--- 235 unchanged lines hidden (view full) ---

1470 int err;
1471
1472#ifdef CONFIG_PCI_MSI
1473 if (adapter->intr.type == VMXNET3_IT_MSIX) {
1474 /* we only use 1 MSI-X vector */
1475 err = request_irq(adapter->intr.msix_entries[0].vector,
1476 vmxnet3_intr, 0, adapter->netdev->name,
1477 adapter->netdev);
1349 } else
1350#endif
1351 if (adapter->intr.type == VMXNET3_IT_MSI) {
1478 } else if (adapter->intr.type == VMXNET3_IT_MSI) {
1352 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1353 adapter->netdev->name, adapter->netdev);
1479 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
1480 adapter->netdev->name, adapter->netdev);
1354 } else {
1481 } else
1482#endif
1483 {
1355 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1356 IRQF_SHARED, adapter->netdev->name,
1357 adapter->netdev);
1358 }
1359
1360 if (err)
1361 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
1362 ":%d\n", adapter->netdev->name, adapter->intr.type, err);

--- 44 unchanged lines hidden (view full) ---

1407 free_irq(adapter->pdev->irq, adapter->netdev);
1408 break;
1409 default:
1410 BUG_ON(true);
1411 }
1412}
1413
1414
1484 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
1485 IRQF_SHARED, adapter->netdev->name,
1486 adapter->netdev);
1487 }
1488
1489 if (err)
1490 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
1491 ":%d\n", adapter->netdev->name, adapter->intr.type, err);

--- 44 unchanged lines hidden (view full) ---

1536 free_irq(adapter->pdev->irq, adapter->netdev);
1537 break;
1538 default:
1539 BUG_ON(true);
1540 }
1541}
1542
1543
1544inline void set_flag_le16(__le16 *data, u16 flag)
1545{
1546 *data = cpu_to_le16(le16_to_cpu(*data) | flag);
1547}
1548
1549inline void set_flag_le64(__le64 *data, u64 flag)
1550{
1551 *data = cpu_to_le64(le64_to_cpu(*data) | flag);
1552}
1553
1554inline void reset_flag_le64(__le64 *data, u64 flag)
1555{
1556 *data = cpu_to_le64(le64_to_cpu(*data) & ~flag);
1557}
1558
1559
1415static void
1416vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
1417{
1418 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1419 struct Vmxnet3_DriverShared *shared = adapter->shared;
1420 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1421
1422 if (grp) {
1423 /* add vlan rx stripping. */
1424 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) {
1425 int i;
1426 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
1427 adapter->vlan_grp = grp;
1428
1429 /* update FEATURES to device */
1560static void
1561vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
1562{
1563 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1564 struct Vmxnet3_DriverShared *shared = adapter->shared;
1565 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
1566
1567 if (grp) {
1568 /* add vlan rx stripping. */
1569 if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) {
1570 int i;
1571 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
1572 adapter->vlan_grp = grp;
1573
1574 /* update FEATURES to device */
1430 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1575 set_flag_le64(&devRead->misc.uptFeatures,
1576 UPT1_F_RXVLAN);
1431 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1432 VMXNET3_CMD_UPDATE_FEATURE);
1433 /*
1434 * Clear entire vfTable; then enable untagged pkts.
1435 * Note: setting one entry in vfTable to non-zero turns
1436 * on VLAN rx filtering.
1437 */
1438 for (i = 0; i < VMXNET3_VFT_SIZE; i++)

--- 6 unchanged lines hidden (view full) ---

1445 printk(KERN_ERR "%s: vlan_rx_register when device has "
1446 "no NETIF_F_HW_VLAN_RX\n", netdev->name);
1447 }
1448 } else {
1449 /* remove vlan rx stripping. */
1450 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
1451 adapter->vlan_grp = NULL;
1452
1577 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1578 VMXNET3_CMD_UPDATE_FEATURE);
1579 /*
1580 * Clear entire vfTable; then enable untagged pkts.
1581 * Note: setting one entry in vfTable to non-zero turns
1582 * on VLAN rx filtering.
1583 */
1584 for (i = 0; i < VMXNET3_VFT_SIZE; i++)

--- 6 unchanged lines hidden (view full) ---

1591 printk(KERN_ERR "%s: vlan_rx_register when device has "
1592 "no NETIF_F_HW_VLAN_RX\n", netdev->name);
1593 }
1594 } else {
1595 /* remove vlan rx stripping. */
1596 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
1597 adapter->vlan_grp = NULL;
1598
1453 if (devRead->misc.uptFeatures & UPT1_F_RXVLAN) {
1599 if (le64_to_cpu(devRead->misc.uptFeatures) & UPT1_F_RXVLAN) {
1454 int i;
1455
1456 for (i = 0; i < VMXNET3_VFT_SIZE; i++) {
1457 /* clear entire vfTable; this also disables
1458 * VLAN rx filtering
1459 */
1460 vfTable[i] = 0;
1461 }
1462 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1463 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1464
1465 /* update FEATURES to device */
1600 int i;
1601
1602 for (i = 0; i < VMXNET3_VFT_SIZE; i++) {
1603 /* clear entire vfTable; this also disables
1604 * VLAN rx filtering
1605 */
1606 vfTable[i] = 0;
1607 }
1608 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1609 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1610
1611 /* update FEATURES to device */
1466 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1612 reset_flag_le64(&devRead->misc.uptFeatures,
1613 UPT1_F_RXVLAN);
1467 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1468 VMXNET3_CMD_UPDATE_FEATURE);
1469 }
1470 }
1471}
1472
1473
1474static void

--- 85 unchanged lines hidden (view full) ---

1560
1561 if (netdev->flags & IFF_ALLMULTI)
1562 new_mode |= VMXNET3_RXM_ALL_MULTI;
1563 else
1564 if (netdev->mc_count > 0) {
1565 new_table = vmxnet3_copy_mc(netdev);
1566 if (new_table) {
1567 new_mode |= VMXNET3_RXM_MCAST;
1614 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1615 VMXNET3_CMD_UPDATE_FEATURE);
1616 }
1617 }
1618}
1619
1620
1621static void

--- 85 unchanged lines hidden (view full) ---

1707
1708 if (netdev->flags & IFF_ALLMULTI)
1709 new_mode |= VMXNET3_RXM_ALL_MULTI;
1710 else
1711 if (netdev->mc_count > 0) {
1712 new_table = vmxnet3_copy_mc(netdev);
1713 if (new_table) {
1714 new_mode |= VMXNET3_RXM_MCAST;
1568 rxConf->mfTableLen = netdev->mc_count *
1569 ETH_ALEN;
1570 rxConf->mfTablePA = virt_to_phys(new_table);
1715 rxConf->mfTableLen = cpu_to_le16(
1716 netdev->mc_count * ETH_ALEN);
1717 rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
1718 new_table));
1571 } else {
1572 printk(KERN_INFO "%s: failed to copy mcast list"
1573 ", setting ALL_MULTI\n", netdev->name);
1574 new_mode |= VMXNET3_RXM_ALL_MULTI;
1575 }
1576 }
1577
1578
1579 if (!(new_mode & VMXNET3_RXM_MCAST)) {
1580 rxConf->mfTableLen = 0;
1581 rxConf->mfTablePA = 0;
1582 }
1583
1584 if (new_mode != rxConf->rxMode) {
1719 } else {
1720 printk(KERN_INFO "%s: failed to copy mcast list"
1721 ", setting ALL_MULTI\n", netdev->name);
1722 new_mode |= VMXNET3_RXM_ALL_MULTI;
1723 }
1724 }
1725
1726
1727 if (!(new_mode & VMXNET3_RXM_MCAST)) {
1728 rxConf->mfTableLen = 0;
1729 rxConf->mfTablePA = 0;
1730 }
1731
1732 if (new_mode != rxConf->rxMode) {
1585 rxConf->rxMode = new_mode;
1733 rxConf->rxMode = cpu_to_le32(new_mode);
1586 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1587 VMXNET3_CMD_UPDATE_RX_MODE);
1588 }
1589
1590 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1591 VMXNET3_CMD_UPDATE_MAC_FILTERS);
1592
1593 kfree(new_table);

--- 11 unchanged lines hidden (view full) ---

1605 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
1606 struct Vmxnet3_TxQueueConf *tqc;
1607 struct Vmxnet3_RxQueueConf *rqc;
1608 int i;
1609
1610 memset(shared, 0, sizeof(*shared));
1611
1612 /* driver settings */
1734 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1735 VMXNET3_CMD_UPDATE_RX_MODE);
1736 }
1737
1738 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1739 VMXNET3_CMD_UPDATE_MAC_FILTERS);
1740
1741 kfree(new_table);

--- 11 unchanged lines hidden (view full) ---

1753 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
1754 struct Vmxnet3_TxQueueConf *tqc;
1755 struct Vmxnet3_RxQueueConf *rqc;
1756 int i;
1757
1758 memset(shared, 0, sizeof(*shared));
1759
1760 /* driver settings */
1613 shared->magic = VMXNET3_REV1_MAGIC;
1614 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
1761 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
1762 devRead->misc.driverInfo.version = cpu_to_le32(
1763 VMXNET3_DRIVER_VERSION_NUM);
1615 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
1616 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
1617 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
1764 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
1765 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
1766 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
1618 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
1619 devRead->misc.driverInfo.uptVerSpt = 1;
1767 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
1768 *((u32 *)&devRead->misc.driverInfo.gos));
1769 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
1770 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
1620
1771
1621 devRead->misc.ddPA = virt_to_phys(adapter);
1622 devRead->misc.ddLen = sizeof(struct vmxnet3_adapter);
1772 devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
1773 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
1623
1624 /* set up feature flags */
1625 if (adapter->rxcsum)
1774
1775 /* set up feature flags */
1776 if (adapter->rxcsum)
1626 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
1777 set_flag_le64(&devRead->misc.uptFeatures, UPT1_F_RXCSUM);
1627
1628 if (adapter->lro) {
1778
1779 if (adapter->lro) {
1629 devRead->misc.uptFeatures |= UPT1_F_LRO;
1630 devRead->misc.maxNumRxSG = 1 + MAX_SKB_FRAGS;
1780 set_flag_le64(&devRead->misc.uptFeatures, UPT1_F_LRO);
1781 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
1631 }
1782 }
1632 if ((adapter->netdev->features & NETIF_F_HW_VLAN_RX)
1633 && adapter->vlan_grp) {
1634 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1783 if ((adapter->netdev->features & NETIF_F_HW_VLAN_RX) &&
1784 adapter->vlan_grp) {
1785 set_flag_le64(&devRead->misc.uptFeatures, UPT1_F_RXVLAN);
1635 }
1636
1786 }
1787
1637 devRead->misc.mtu = adapter->netdev->mtu;
1638 devRead->misc.queueDescPA = adapter->queue_desc_pa;
1639 devRead->misc.queueDescLen = sizeof(struct Vmxnet3_TxQueueDesc) +
1640 sizeof(struct Vmxnet3_RxQueueDesc);
1788 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
1789 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
1790 devRead->misc.queueDescLen = cpu_to_le32(
1791 sizeof(struct Vmxnet3_TxQueueDesc) +
1792 sizeof(struct Vmxnet3_RxQueueDesc));
1641
1642 /* tx queue settings */
1643 BUG_ON(adapter->tx_queue.tx_ring.base == NULL);
1644
1645 devRead->misc.numTxQueues = 1;
1646 tqc = &adapter->tqd_start->conf;
1793
1794 /* tx queue settings */
1795 BUG_ON(adapter->tx_queue.tx_ring.base == NULL);
1796
1797 devRead->misc.numTxQueues = 1;
1798 tqc = &adapter->tqd_start->conf;
1647 tqc->txRingBasePA = adapter->tx_queue.tx_ring.basePA;
1648 tqc->dataRingBasePA = adapter->tx_queue.data_ring.basePA;
1649 tqc->compRingBasePA = adapter->tx_queue.comp_ring.basePA;
1650 tqc->ddPA = virt_to_phys(adapter->tx_queue.buf_info);
1651 tqc->txRingSize = adapter->tx_queue.tx_ring.size;
1652 tqc->dataRingSize = adapter->tx_queue.data_ring.size;
1653 tqc->compRingSize = adapter->tx_queue.comp_ring.size;
1654 tqc->ddLen = sizeof(struct vmxnet3_tx_buf_info) *
1655 tqc->txRingSize;
1799 tqc->txRingBasePA = cpu_to_le64(adapter->tx_queue.tx_ring.basePA);
1800 tqc->dataRingBasePA = cpu_to_le64(adapter->tx_queue.data_ring.basePA);
1801 tqc->compRingBasePA = cpu_to_le64(adapter->tx_queue.comp_ring.basePA);
1802 tqc->ddPA = cpu_to_le64(virt_to_phys(
1803 adapter->tx_queue.buf_info));
1804 tqc->txRingSize = cpu_to_le32(adapter->tx_queue.tx_ring.size);
1805 tqc->dataRingSize = cpu_to_le32(adapter->tx_queue.data_ring.size);
1806 tqc->compRingSize = cpu_to_le32(adapter->tx_queue.comp_ring.size);
1807 tqc->ddLen = cpu_to_le32(sizeof(struct vmxnet3_tx_buf_info) *
1808 tqc->txRingSize);
1656 tqc->intrIdx = adapter->tx_queue.comp_ring.intr_idx;
1657
1658 /* rx queue settings */
1659 devRead->misc.numRxQueues = 1;
1660 rqc = &adapter->rqd_start->conf;
1809 tqc->intrIdx = adapter->tx_queue.comp_ring.intr_idx;
1810
1811 /* rx queue settings */
1812 devRead->misc.numRxQueues = 1;
1813 rqc = &adapter->rqd_start->conf;
1661 rqc->rxRingBasePA[0] = adapter->rx_queue.rx_ring[0].basePA;
1662 rqc->rxRingBasePA[1] = adapter->rx_queue.rx_ring[1].basePA;
1663 rqc->compRingBasePA = adapter->rx_queue.comp_ring.basePA;
1664 rqc->ddPA = virt_to_phys(adapter->rx_queue.buf_info);
1665 rqc->rxRingSize[0] = adapter->rx_queue.rx_ring[0].size;
1666 rqc->rxRingSize[1] = adapter->rx_queue.rx_ring[1].size;
1667 rqc->compRingSize = adapter->rx_queue.comp_ring.size;
1668 rqc->ddLen = sizeof(struct vmxnet3_rx_buf_info) *
1669 (rqc->rxRingSize[0] + rqc->rxRingSize[1]);
1814 rqc->rxRingBasePA[0] = cpu_to_le64(adapter->rx_queue.rx_ring[0].basePA);
1815 rqc->rxRingBasePA[1] = cpu_to_le64(adapter->rx_queue.rx_ring[1].basePA);
1816 rqc->compRingBasePA = cpu_to_le64(adapter->rx_queue.comp_ring.basePA);
1817 rqc->ddPA = cpu_to_le64(virt_to_phys(
1818 adapter->rx_queue.buf_info));
1819 rqc->rxRingSize[0] = cpu_to_le32(adapter->rx_queue.rx_ring[0].size);
1820 rqc->rxRingSize[1] = cpu_to_le32(adapter->rx_queue.rx_ring[1].size);
1821 rqc->compRingSize = cpu_to_le32(adapter->rx_queue.comp_ring.size);
1822 rqc->ddLen = cpu_to_le32(sizeof(struct vmxnet3_rx_buf_info) *
1823 (rqc->rxRingSize[0] + rqc->rxRingSize[1]));
1670 rqc->intrIdx = adapter->rx_queue.comp_ring.intr_idx;
1671
1672 /* intr settings */
1673 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
1674 VMXNET3_IMM_AUTO;
1675 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
1676 for (i = 0; i < adapter->intr.num_intrs; i++)
1677 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];

--- 32 unchanged lines hidden (view full) ---

1710 if (err) {
1711 printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
1712 adapter->netdev->name, err);
1713 goto irq_err;
1714 }
1715
1716 vmxnet3_setup_driver_shared(adapter);
1717
1824 rqc->intrIdx = adapter->rx_queue.comp_ring.intr_idx;
1825
1826 /* intr settings */
1827 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
1828 VMXNET3_IMM_AUTO;
1829 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
1830 for (i = 0; i < adapter->intr.num_intrs; i++)
1831 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];

--- 32 unchanged lines hidden (view full) ---

1864 if (err) {
1865 printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
1866 adapter->netdev->name, err);
1867 goto irq_err;
1868 }
1869
1870 vmxnet3_setup_driver_shared(adapter);
1871
1718 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL,
1719 VMXNET3_GET_ADDR_LO(adapter->shared_pa));
1720 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH,
1721 VMXNET3_GET_ADDR_HI(adapter->shared_pa));
1722
1872 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
1873 adapter->shared_pa));
1874 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
1875 adapter->shared_pa));
1723 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1724 VMXNET3_CMD_ACTIVATE_DEV);
1725 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
1726
1727 if (ret != 0) {
1728 printk(KERN_ERR "Failed to activate dev %s: error %u\n",
1729 adapter->netdev->name, ret);
1730 err = -EINVAL;

--- 689 unchanged lines hidden (view full) ---

2420 memset(pmConf, 0, sizeof(*pmConf));
2421
2422 if (adapter->wol & WAKE_UCAST) {
2423 pmConf->filters[i].patternSize = ETH_ALEN;
2424 pmConf->filters[i].maskSize = 1;
2425 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
2426 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
2427
1876 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
1877 VMXNET3_CMD_ACTIVATE_DEV);
1878 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
1879
1880 if (ret != 0) {
1881 printk(KERN_ERR "Failed to activate dev %s: error %u\n",
1882 adapter->netdev->name, ret);
1883 err = -EINVAL;

--- 689 unchanged lines hidden (view full) ---

2573 memset(pmConf, 0, sizeof(*pmConf));
2574
2575 if (adapter->wol & WAKE_UCAST) {
2576 pmConf->filters[i].patternSize = ETH_ALEN;
2577 pmConf->filters[i].maskSize = 1;
2578 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
2579 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
2580
2428 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
2581 set_flag_le16(&pmConf->wakeUpEvents, VMXNET3_PM_WAKEUP_FILTER);
2429 i++;
2430 }
2431
2432 if (adapter->wol & WAKE_ARP) {
2433 in_dev = in_dev_get(netdev);
2434 if (!in_dev)
2435 goto skip_arp;
2436

--- 25 unchanged lines hidden (view full) ---

2462 pmConf->filters[i].mask[0] = 0x00;
2463 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
2464 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
2465 pmConf->filters[i].mask[3] = 0x00;
2466 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
2467 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
2468 in_dev_put(in_dev);
2469
2582 i++;
2583 }
2584
2585 if (adapter->wol & WAKE_ARP) {
2586 in_dev = in_dev_get(netdev);
2587 if (!in_dev)
2588 goto skip_arp;
2589

--- 25 unchanged lines hidden (view full) ---

2615 pmConf->filters[i].mask[0] = 0x00;
2616 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
2617 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
2618 pmConf->filters[i].mask[3] = 0x00;
2619 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
2620 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
2621 in_dev_put(in_dev);
2622
2470 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
2623 set_flag_le16(&pmConf->wakeUpEvents, VMXNET3_PM_WAKEUP_FILTER);
2471 i++;
2472 }
2473
2474skip_arp:
2475 if (adapter->wol & WAKE_MAGIC)
2624 i++;
2625 }
2626
2627skip_arp:
2628 if (adapter->wol & WAKE_MAGIC)
2476 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
2629 set_flag_le16(&pmConf->wakeUpEvents, VMXNET3_PM_WAKEUP_MAGIC);
2477
2478 pmConf->numFilters = i;
2479
2630
2631 pmConf->numFilters = i;
2632
2480 adapter->shared->devRead.pmConfDesc.confVer = 1;
2481 adapter->shared->devRead.pmConfDesc.confLen = sizeof(*pmConf);
2482 adapter->shared->devRead.pmConfDesc.confPA = virt_to_phys(pmConf);
2633 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
2634 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
2635 *pmConf));
2636 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
2637 pmConf));
2483
2484 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2485 VMXNET3_CMD_UPDATE_PMCFG);
2486
2487 pci_save_state(pdev);
2488 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
2489 adapter->wol);
2490 pci_disable_device(pdev);

--- 14 unchanged lines hidden (view full) ---

2505
2506 if (!netif_running(netdev))
2507 return 0;
2508
2509 /* Destroy wake-up filters. */
2510 pmConf = adapter->pm_conf;
2511 memset(pmConf, 0, sizeof(*pmConf));
2512
2638
2639 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2640 VMXNET3_CMD_UPDATE_PMCFG);
2641
2642 pci_save_state(pdev);
2643 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
2644 adapter->wol);
2645 pci_disable_device(pdev);

--- 14 unchanged lines hidden (view full) ---

2660
2661 if (!netif_running(netdev))
2662 return 0;
2663
2664 /* Destroy wake-up filters. */
2665 pmConf = adapter->pm_conf;
2666 memset(pmConf, 0, sizeof(*pmConf));
2667
2513 adapter->shared->devRead.pmConfDesc.confVer = 1;
2514 adapter->shared->devRead.pmConfDesc.confLen = sizeof(*pmConf);
2515 adapter->shared->devRead.pmConfDesc.confPA = virt_to_phys(pmConf);
2668 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
2669 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
2670 *pmConf));
2671 adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le32(virt_to_phys(
2672 pmConf));
2516
2517 netif_device_attach(netdev);
2518 pci_set_power_state(pdev, PCI_D0);
2519 pci_restore_state(pdev);
2520 err = pci_enable_device_mem(pdev);
2521 if (err != 0)
2522 return err;
2523

--- 51 unchanged lines hidden --- 		2673
2674 netif_device_attach(netdev);
2675 pci_set_power_state(pdev, PCI_D0);
2676 pci_restore_state(pdev);
2677 err = pci_enable_device_mem(pdev);
2678 if (err != 0)
2679 return err;
2680

--- 51 unchanged lines hidden ---