at803x.c (9e56ff53b4115875667760445b028357848b4748) at803x.c (6fb760972c49490b03f3db2ad64cf30bdd28c54a)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */

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17#include <linux/regulator/of_regulator.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of.h>
21#include <linux/phylink.h>
22#include <linux/sfp.h>
23#include <dt-bindings/net/qca-ar803x.h>
24
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */

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17#include <linux/regulator/of_regulator.h>
18#include <linux/regulator/driver.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of.h>
21#include <linux/phylink.h>
22#include <linux/sfp.h>
23#include <dt-bindings/net/qca-ar803x.h>
24
25#include "qcom.h"
26
25#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
26#define AT803X_SFC_ASSERT_CRS BIT(11)
27#define AT803X_SFC_FORCE_LINK BIT(10)
28#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
29#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
30#define AT803X_SFC_MANUAL_MDIX 0x1
31#define AT803X_SFC_MANUAL_MDI 0x0
32#define AT803X_SFC_SQE_TEST BIT(2)

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79#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
80#define AT803X_WOL_EN BIT(5)
81#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
82#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
83#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
84#define AT803X_REG_CHIP_CONFIG 0x1f
85#define AT803X_BT_BX_REG_SEL 0x8000
86
27#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
28#define AT803X_SFC_ASSERT_CRS BIT(11)
29#define AT803X_SFC_FORCE_LINK BIT(10)
30#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
31#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
32#define AT803X_SFC_MANUAL_MDIX 0x1
33#define AT803X_SFC_MANUAL_MDI 0x0
34#define AT803X_SFC_SQE_TEST BIT(2)

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81#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
82#define AT803X_WOL_EN BIT(5)
83#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
84#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
85#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
86#define AT803X_REG_CHIP_CONFIG 0x1f
87#define AT803X_BT_BX_REG_SEL 0x8000
88
87#define AT803X_DEBUG_ADDR 0x1D
88#define AT803X_DEBUG_DATA 0x1E
89
90#define AT803X_MODE_CFG_MASK 0x0F
91#define AT803X_MODE_CFG_BASET_RGMII 0x00
92#define AT803X_MODE_CFG_BASET_SGMII 0x01
93#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
94#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
95#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
96#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
97#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
98#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
99#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
100#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
101#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
102
103#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
104#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
105
89#define AT803X_MODE_CFG_MASK 0x0F
90#define AT803X_MODE_CFG_BASET_RGMII 0x00
91#define AT803X_MODE_CFG_BASET_SGMII 0x01
92#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
93#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
94#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
95#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
96#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
97#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
98#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
99#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
100#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
101
102#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
103#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
104
106#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
107#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
108#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
109#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
110
111#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
112#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
113
114#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
115#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
116#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
117#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
118
119#define AT803X_DEBUG_REG_3C 0x3C
120
121#define AT803X_DEBUG_REG_GREEN 0x3D
122#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
123
124#define AT803X_DEBUG_REG_1F 0x1F
125#define AT803X_DEBUG_PLL_ON BIT(2)
126#define AT803X_DEBUG_RGMII_1V8 BIT(3)

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388
389#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
390#define QCA8081_PHY_FIFO_RSTN BIT(11)
391
392MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
393MODULE_AUTHOR("Matus Ujhelyi");
394MODULE_LICENSE("GPL");
395
105#define AT803X_DEBUG_REG_3C 0x3C
106
107#define AT803X_DEBUG_REG_GREEN 0x3D
108#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
109
110#define AT803X_DEBUG_REG_1F 0x1F
111#define AT803X_DEBUG_PLL_ON BIT(2)
112#define AT803X_DEBUG_RGMII_1V8 BIT(3)

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374
375#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
376#define QCA8081_PHY_FIFO_RSTN BIT(11)
377
378MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
379MODULE_AUTHOR("Matus Ujhelyi");
380MODULE_LICENSE("GPL");
381
396enum stat_access_type {
397 PHY,
398 MMD
399};
400
401struct at803x_hw_stat {
402 const char *string;
403 u8 reg;
404 u32 mask;
405 enum stat_access_type access_type;
406};
407
408static struct at803x_hw_stat qca83xx_hw_stats[] = {
409 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
410 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
411 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
412};
413
414struct at803x_ss_mask {
415 u16 speed_mask;

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434 u16 bmcr;
435 u16 advertise;
436 u16 control1000;
437 u16 int_enable;
438 u16 smart_speed;
439 u16 led_control;
440};
441
382static struct at803x_hw_stat qca83xx_hw_stats[] = {
383 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
384 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
385 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
386};
387
388struct at803x_ss_mask {
389 u16 speed_mask;

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408 u16 bmcr;
409 u16 advertise;
410 u16 control1000;
411 u16 int_enable;
412 u16 smart_speed;
413 u16 led_control;
414};
415
442static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
443{
444 int ret;
445
446 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
447 if (ret < 0)
448 return ret;
449
450 return phy_write(phydev, AT803X_DEBUG_DATA, data);
451}
452
453static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
454{
455 int ret;
456
457 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
458 if (ret < 0)
459 return ret;
460
461 return phy_read(phydev, AT803X_DEBUG_DATA);
462}
463
464static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
465 u16 clear, u16 set)
466{
467 u16 val;
468 int ret;
469
470 ret = at803x_debug_reg_read(phydev, reg);
471 if (ret < 0)
472 return ret;
473
474 val = ret & 0xffff;
475 val &= ~clear;
476 val |= set;
477
478 return phy_write(phydev, AT803X_DEBUG_DATA, val);
479}
480
481static int at803x_write_page(struct phy_device *phydev, int page)
482{
483 int mask;
484 int set;
485
486 if (page == AT803X_PAGE_COPPER) {
487 set = AT803X_BT_BX_REG_SEL;
488 mask = 0;

--- 2271 unchanged lines hidden --- 		416static int at803x_write_page(struct phy_device *phydev, int page)
417{
418 int mask;
419 int set;
420
421 if (page == AT803X_PAGE_COPPER) {
422 set = AT803X_BT_BX_REG_SEL;
423 mask = 0;

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