marvell10g.c (639136d2a70ab9837befb22ad5b3d67cb4db2216) marvell10g.c (05ca1b327eed2b9abb48cbd013ca451032bd86b0)
1/*
2 * Marvell 10G 88x3310 PHY driver
3 *
4 * Based upon the ID registers, this PHY appears to be a mixture of IPs
5 * from two different companies.
6 *
7 * There appears to be several different data paths through the PHY which
8 * are automatically managed by the PHY. The following has been determined
1/*
2 * Marvell 10G 88x3310 PHY driver
3 *
4 * Based upon the ID registers, this PHY appears to be a mixture of IPs
5 * from two different companies.
6 *
7 * There appears to be several different data paths through the PHY which
8 * are automatically managed by the PHY. The following has been determined
9 * via observation and experimentation:
9 * via observation and experimentation for a setup using single-lane Serdes:
10 *
11 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
12 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
13 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
14 *
10 *
11 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
12 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
13 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
14 *
15 * With XAUI, observation shows:
16 *
17 * XAUI PHYXS -- <appropriate PCS as above>
18 *
19 * and no switching of the host interface mode occurs.
20 *
15 * If both the fiber and copper ports are connected, the first to gain
16 * link takes priority and the other port is completely locked out.
17 */
18#include <linux/phy.h>
19#include <linux/marvell_phy.h>
20
21enum {
22 MV_PCS_BASE_T = 0x0000,

--- 56 unchanged lines hidden (view full) ---

79static int mv3310_config_init(struct phy_device *phydev)
80{
81 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
82 u32 mask;
83 int val;
84
85 /* Check that the PHY interface type is compatible */
86 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
21 * If both the fiber and copper ports are connected, the first to gain
22 * link takes priority and the other port is completely locked out.
23 */
24#include <linux/phy.h>
25#include <linux/marvell_phy.h>
26
27enum {
28 MV_PCS_BASE_T = 0x0000,

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85static int mv3310_config_init(struct phy_device *phydev)
86{
87 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
88 u32 mask;
89 int val;
90
91 /* Check that the PHY interface type is compatible */
92 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
87 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
88 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
89 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
90 phydev->interface != PHY_INTERFACE_MODE_10GKR)
91 return -ENODEV;
92
93 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
94 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
95

--- 274 unchanged lines hidden --- 		93 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
94 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
95 phydev->interface != PHY_INTERFACE_MODE_10GKR)
96 return -ENODEV;
97
98 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
99 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
100

--- 274 unchanged lines hidden ---