ipa_reg.h (322053105f09513da0546ca36942fceec473982a) ipa_reg.h (716a115b4f5c78c2919437bf875fc3ba46087c57)
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2020 Linaro Ltd.
5 */
6#ifndef _IPA_REG_H_
7#define _IPA_REG_H_
8

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60 * field mask values. In such cases an inline_function(ipa) is used rather
61 * than a MACRO to define the offset or field mask to use.
62 *
63 * Finally, some registers hold bitmasks representing endpoints. In such
64 * cases the @available field in the @ipa structure defines the "full" set
65 * of valid bits for the register.
66 */
67
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2020 Linaro Ltd.
5 */
6#ifndef _IPA_REG_H_
7#define _IPA_REG_H_
8

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60 * field mask values. In such cases an inline_function(ipa) is used rather
61 * than a MACRO to define the offset or field mask to use.
62 *
63 * Finally, some registers hold bitmasks representing endpoints. In such
64 * cases the @available field in the @ipa structure defines the "full" set
65 * of valid bits for the register.
66 */
67
68#define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038
69
70/* The next field is not supported for IPA v4.1 */
71#define IPA_REG_COMP_CFG_OFFSET 0x0000003c
72#define ENABLE_FMASK GENMASK(0, 0)
73#define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1)
74#define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2)
75#define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3)
76#define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4)
77/* The remaining fields are not present for IPA v3.5.1 */

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243#define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11)
244#define PA_MASK_EN_FMASK GENMASK(12, 12)
245#define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13)
246/* The next two fields are present for IPA v4.2 only */
247#define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18)
248#define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19)
249
250#define IPA_REG_FLAVOR_0_OFFSET 0x00000210
68/* The next field is not supported for IPA v4.1 */
69#define IPA_REG_COMP_CFG_OFFSET 0x0000003c
70#define ENABLE_FMASK GENMASK(0, 0)
71#define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1)
72#define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2)
73#define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3)
74#define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4)
75/* The remaining fields are not present for IPA v3.5.1 */

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241#define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11)
242#define PA_MASK_EN_FMASK GENMASK(12, 12)
243#define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13)
244/* The next two fields are present for IPA v4.2 only */
245#define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18)
246#define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19)
247
248#define IPA_REG_FLAVOR_0_OFFSET 0x00000210
251#define BAM_MAX_PIPES_FMASK GENMASK(4, 0)
252#define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8)
253#define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16)
254#define BAM_PROD_LOWEST_FMASK GENMASK(27, 24)
249#define IPA_MAX_PIPES_FMASK GENMASK(3, 0)
250#define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8)
251#define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16)
252#define IPA_PROD_LOWEST_FMASK GENMASK(27, 24)
255
256static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version)
257{
258 if (version == IPA_VERSION_4_2)
259 return 0x00000240;
260
261 return 0x00000220;
262}

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333#define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3)
334#define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8)
335
336/** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */
337enum ipa_cs_offload_en {
338 IPA_CS_OFFLOAD_NONE = 0x0,
339 IPA_CS_OFFLOAD_UL = 0x1,
340 IPA_CS_OFFLOAD_DL = 0x2,
253
254static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version)
255{
256 if (version == IPA_VERSION_4_2)
257 return 0x00000240;
258
259 return 0x00000220;
260}

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331#define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3)
332#define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8)
333
334/** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */
335enum ipa_cs_offload_en {
336 IPA_CS_OFFLOAD_NONE = 0x0,
337 IPA_CS_OFFLOAD_UL = 0x1,
338 IPA_CS_OFFLOAD_DL = 0x2,
341 IPA_CS_RSVD = 0x3,
342};
343
344#define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \
345 (0x00000810 + 0x0070 * (ep))
346#define HDR_LEN_FMASK GENMASK(5, 0)
347#define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6)
348#define HDR_OFST_METADATA_FMASK GENMASK(12, 7)
349#define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13)

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424/* The next two fields are present for IPA v4.2 only */
425#define BASE_VALUE_FMASK GENMASK(4, 0)
426#define SCALE_FMASK GENMASK(12, 8)
427
428/* Valid only for TX (IPA consumer) endpoints */
429#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \
430 (0x00000834 + 0x0070 * (txep))
431#define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0)
339};
340
341#define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \
342 (0x00000810 + 0x0070 * (ep))
343#define HDR_LEN_FMASK GENMASK(5, 0)
344#define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6)
345#define HDR_OFST_METADATA_FMASK GENMASK(12, 7)
346#define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13)

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421/* The next two fields are present for IPA v4.2 only */
422#define BASE_VALUE_FMASK GENMASK(4, 0)
423#define SCALE_FMASK GENMASK(12, 8)
424
425/* Valid only for TX (IPA consumer) endpoints */
426#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \
427 (0x00000834 + 0x0070 * (txep))
428#define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0)
429#define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6)
432#define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7)
433#define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8)
430#define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7)
431#define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8)
432#define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14)
434#define MAX_PACKET_LEN_FMASK GENMASK(31, 16)
435
436#define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \
437 (0x00000838 + 0x0070 * (ep))
438/* Encoded value for RSRC_GRP endpoint register RSRC_GRP field */
439static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp)
440{
441 switch (version) {

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452#define HPS_SEQ_TYPE_FMASK GENMASK(3, 0)
453#define DPS_SEQ_TYPE_FMASK GENMASK(7, 4)
454#define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8)
455#define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12)
456
457/**
458 * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N
459 * @IPA_SEQ_DMA_ONLY: only DMA is performed
433#define MAX_PACKET_LEN_FMASK GENMASK(31, 16)
434
435#define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \
436 (0x00000838 + 0x0070 * (ep))
437/* Encoded value for RSRC_GRP endpoint register RSRC_GRP field */
438static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp)
439{
440 switch (version) {

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451#define HPS_SEQ_TYPE_FMASK GENMASK(3, 0)
452#define DPS_SEQ_TYPE_FMASK GENMASK(7, 4)
453#define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8)
454#define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12)
455
456/**
457 * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N
458 * @IPA_SEQ_DMA_ONLY: only DMA is performed
460 * @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP:
461 * packet processing + no decipher + microcontroller (Ethernet Bridging)
462 * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP:
463 * second packet processing pass + no decipher + microcontroller
459 * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP:
460 * second packet processing pass + no decipher + microcontroller
464 * @IPA_SEQ_DMA_DEC: DMA + cipher/decipher
465 * @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression
466 * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP:
467 * packet processing + no decipher + no uCP + HPS REP DMA parser
468 * @IPA_SEQ_INVALID: invalid sequencer type
469 *
470 * The values defined here are broken into 4-bit nibbles that are written
471 * into fields of the INIT_SEQ_N endpoint registers.
472 */
473enum ipa_seq_type {
474 IPA_SEQ_DMA_ONLY = 0x0000,
461 * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP:
462 * packet processing + no decipher + no uCP + HPS REP DMA parser
463 * @IPA_SEQ_INVALID: invalid sequencer type
464 *
465 * The values defined here are broken into 4-bit nibbles that are written
466 * into fields of the INIT_SEQ_N endpoint registers.
467 */
468enum ipa_seq_type {
469 IPA_SEQ_DMA_ONLY = 0x0000,
475 IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002,
476 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004,
470 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004,
477 IPA_SEQ_DMA_DEC = 0x0011,
478 IPA_SEQ_DMA_COMP_DECOMP = 0x0020,
479 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806,
480 IPA_SEQ_INVALID = 0xffff,
481};
482
483#define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \
484 (0x00000840 + 0x0070 * (ep))
485#define STATUS_EN_FMASK GENMASK(0, 0)
486#define STATUS_ENDP_FMASK GENMASK(5, 1)

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560 IPA_IRQ_GSI_UC = 0x19,
561 IPA_IRQ_COUNT, /* Last; not an id */
562};
563
564#define IPA_REG_IRQ_UC_OFFSET \
565 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP)
566#define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \
567 (0x0000301c + 0x1000 * (ee))
471 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806,
472 IPA_SEQ_INVALID = 0xffff,
473};
474
475#define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \
476 (0x00000840 + 0x0070 * (ep))
477#define STATUS_EN_FMASK GENMASK(0, 0)
478#define STATUS_ENDP_FMASK GENMASK(5, 1)

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552 IPA_IRQ_GSI_UC = 0x19,
553 IPA_IRQ_COUNT, /* Last; not an id */
554};
555
556#define IPA_REG_IRQ_UC_OFFSET \
557 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP)
558#define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \
559 (0x0000301c + 0x1000 * (ee))
560#define UC_INTR_FMASK GENMASK(0, 0)
568
569/* ipa->available defines the valid bits in the SUSPEND_INFO register */
570#define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \
571 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP)
572#define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \
573 (0x00003030 + 0x1000 * (ee))
574
575/* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */

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562/* ipa->available defines the valid bits in the SUSPEND_INFO register */
563#define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \
564 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP)
565#define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \
566 (0x00003030 + 0x1000 * (ee))
567
568/* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */

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