ipa_reg.h (1c418c4a929cae00780429fbceda7e163b5e0f71) ipa_reg.h (4468a3448b6aa1c00f25ce1162c57d4a7c2e7ba2)
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2021 Linaro Ltd.
5 */
6#ifndef _IPA_REG_H_
7#define _IPA_REG_H_
8

--- 357 unchanged lines hidden (view full) ---

366enum ipa_reg_rsrc_grp_rsrc_type_field_id {
367 X_MIN_LIM,
368 X_MAX_LIM,
369 Y_MIN_LIM,
370 Y_MAX_LIM,
371};
372
373/* ENDP_INIT_CTRL register */
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2021 Linaro Ltd.
5 */
6#ifndef _IPA_REG_H_
7#define _IPA_REG_H_
8

--- 357 unchanged lines hidden (view full) ---

366enum ipa_reg_rsrc_grp_rsrc_type_field_id {
367 X_MIN_LIM,
368 X_MAX_LIM,
369 Y_MIN_LIM,
370 Y_MAX_LIM,
371};
372
373/* ENDP_INIT_CTRL register */
374/* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */
375#define ENDP_SUSPEND_FMASK GENMASK(0, 0)
376/* Valid only for TX (IPA consumer) endpoints */
377#define ENDP_DELAY_FMASK GENMASK(1, 1)
374enum ipa_reg_endp_init_ctrl_field_id {
375 ENDP_SUSPEND, /* Not v4.0+ */
376 ENDP_DELAY, /* Not v4.2+ */
377};
378
379/* ENDP_INIT_CFG register */
378
379/* ENDP_INIT_CFG register */
380#define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0)
381#define CS_OFFLOAD_EN_FMASK GENMASK(2, 1)
382#define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3)
383#define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8)
380enum ipa_reg_endp_init_cfg_field_id {
381 FRAG_OFFLOAD_EN,
382 CS_OFFLOAD_EN,
383 CS_METADATA_HDR_OFFSET,
384 CS_GEN_QMB_MASTER_SEL,
385};
384
385/** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */
386enum ipa_cs_offload_en {
387 IPA_CS_OFFLOAD_NONE = 0x0,
388 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */
389 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */
390 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */
391};
392
393/* ENDP_INIT_NAT register */
386
387/** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */
388enum ipa_cs_offload_en {
389 IPA_CS_OFFLOAD_NONE = 0x0,
390 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */
391 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */
392 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */
393};
394
395/* ENDP_INIT_NAT register */
394#define NAT_EN_FMASK GENMASK(1, 0)
396enum ipa_reg_endp_init_nat_field_id {
397 NAT_EN,
398};
395
396/** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */
397enum ipa_nat_en {
398 IPA_NAT_BYPASS = 0x0,
399 IPA_NAT_SRC = 0x1,
400 IPA_NAT_DST = 0x2,
401};
402
403/* ENDP_INIT_HDR register */
399
400/** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */
401enum ipa_nat_en {
402 IPA_NAT_BYPASS = 0x0,
403 IPA_NAT_SRC = 0x1,
404 IPA_NAT_DST = 0x2,
405};
406
407/* ENDP_INIT_HDR register */
404#define HDR_LEN_FMASK GENMASK(5, 0)
405#define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6)
406#define HDR_OFST_METADATA_FMASK GENMASK(12, 7)
407#define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13)
408#define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19)
409#define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20)
410/* The next field is not present for IPA v4.9+ */
411#define HDR_A5_MUX_FMASK GENMASK(26, 26)
412#define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27)
413/* The next field is not present for IPA v4.5+ */
414#define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28)
415/* The next two fields are present for IPA v4.5+ */
416#define HDR_LEN_MSB_FMASK GENMASK(29, 28)
417#define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30)
408enum ipa_reg_endp_init_hdr_field_id {
409 HDR_LEN,
410 HDR_OFST_METADATA_VALID,
411 HDR_OFST_METADATA,
412 HDR_ADDITIONAL_CONST_LEN,
413 HDR_OFST_PKT_SIZE_VALID,
414 HDR_OFST_PKT_SIZE,
415 HDR_A5_MUX, /* Not v4.9+ */
416 HDR_LEN_INC_DEAGG_HDR,
417 HDR_METADATA_REG_VALID, /* Not v4.5+ */
418 HDR_LEN_MSB, /* v4.5+ */
419 HDR_OFST_METADATA_MSB, /* v4.5+ */
420};
418
421
419/* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */
420static inline u32 ipa_header_size_encoded(enum ipa_version version,
421 u32 header_size)
422{
423 u32 size = header_size & field_mask(HDR_LEN_FMASK);
424 u32 val;
425
426 val = u32_encode_bits(size, HDR_LEN_FMASK);
427 if (version < IPA_VERSION_4_5) {
428 WARN_ON(header_size != size);
429 return val;
430 }
431
432 /* IPA v4.5 adds a few more most-significant bits */
433 size = header_size >> hweight32(HDR_LEN_FMASK);
434 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK);
435
436 return val;
437}
438
439/* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */
440static inline u32 ipa_metadata_offset_encoded(enum ipa_version version,
441 u32 offset)
442{
443 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK);
444 u32 val;
445
446 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK);
447 if (version < IPA_VERSION_4_5) {
448 WARN_ON(offset != off);
449 return val;
450 }
451
452 /* IPA v4.5 adds a few more most-significant bits */
453 off = offset >> hweight32(HDR_OFST_METADATA_FMASK);
454 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK);
455
456 return val;
457}
458
459/* ENDP_INIT_HDR_EXT register */
422/* ENDP_INIT_HDR_EXT register */
460#define HDR_ENDIANNESS_FMASK GENMASK(0, 0)
461#define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1)
462#define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2)
463#define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3)
464#define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4)
465#define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10)
466/* The next three fields are present for IPA v4.5+ */
467#define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16)
468#define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18)
469#define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20)
423enum ipa_reg_endp_init_hdr_ext_field_id {
424 HDR_ENDIANNESS,
425 HDR_TOTAL_LEN_OR_PAD_VALID,
426 HDR_TOTAL_LEN_OR_PAD,
427 HDR_PAYLOAD_LEN_INC_PADDING,
428 HDR_TOTAL_LEN_OR_PAD_OFFSET,
429 HDR_PAD_TO_ALIGNMENT,
430 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */
431 HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */
432 HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */
433};
470
471/* ENDP_INIT_MODE register */
472#define MODE_FMASK GENMASK(2, 0)
473/* The next field is present for IPA v4.5+ */
474#define DCPH_ENABLE_FMASK GENMASK(3, 3)
475#define DEST_PIPE_INDEX_FMASK GENMASK(8, 4)
476#define BYTE_THRESHOLD_FMASK GENMASK(27, 12)
477#define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28)

--- 337 unchanged lines hidden --- 		434
435/* ENDP_INIT_MODE register */
436#define MODE_FMASK GENMASK(2, 0)
437/* The next field is present for IPA v4.5+ */
438#define DCPH_ENABLE_FMASK GENMASK(3, 3)
439#define DEST_PIPE_INDEX_FMASK GENMASK(8, 4)
440#define BYTE_THRESHOLD_FMASK GENMASK(27, 12)
441#define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28)

--- 337 unchanged lines hidden ---