dwmac4.h (71db1cd7ff4ea3b525ae7d9c97633ea281b7d981) dwmac4.h (4dbbe8dde8485b89bce8bbbe7564337fd7eed69f)
1/*
2 * DWMAC4 Header file.
3 *
4 * Copyright (C) 2015 STMicroelectronics Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.

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29#define GMAC_RXQ_CTRL2 0x000000a8
30#define GMAC_RXQ_CTRL3 0x000000ac
31#define GMAC_INT_STATUS 0x000000b0
32#define GMAC_INT_EN 0x000000b4
33#define GMAC_1US_TIC_COUNTER 0x000000dc
34#define GMAC_PCS_BASE 0x000000e0
35#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
36#define GMAC_PMT 0x000000c0
1/*
2 * DWMAC4 Header file.
3 *
4 * Copyright (C) 2015 STMicroelectronics Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.

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29#define GMAC_RXQ_CTRL2 0x000000a8
30#define GMAC_RXQ_CTRL3 0x000000ac
31#define GMAC_INT_STATUS 0x000000b0
32#define GMAC_INT_EN 0x000000b4
33#define GMAC_1US_TIC_COUNTER 0x000000dc
34#define GMAC_PCS_BASE 0x000000e0
35#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
36#define GMAC_PMT 0x000000c0
37#define GMAC_VERSION 0x00000110
38#define GMAC_DEBUG 0x00000114
39#define GMAC_HW_FEATURE0 0x0000011c
40#define GMAC_HW_FEATURE1 0x00000120
41#define GMAC_HW_FEATURE2 0x00000124
42#define GMAC_HW_FEATURE3 0x00000128
43#define GMAC_MDIO_ADDR 0x00000200
44#define GMAC_MDIO_DATA 0x00000204
45#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)

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190/* MAC HW features2 bitmap */
191#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
192#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
193#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
194#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
195
196/* MAC HW features3 bitmap */
197#define GMAC_HW_FEAT_ASP GENMASK(29, 28)
37#define GMAC_DEBUG 0x00000114
38#define GMAC_HW_FEATURE0 0x0000011c
39#define GMAC_HW_FEATURE1 0x00000120
40#define GMAC_HW_FEATURE2 0x00000124
41#define GMAC_HW_FEATURE3 0x00000128
42#define GMAC_MDIO_ADDR 0x00000200
43#define GMAC_MDIO_DATA 0x00000204
44#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)

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189/* MAC HW features2 bitmap */
190#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
191#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
192#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
193#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
194
195/* MAC HW features3 bitmap */
196#define GMAC_HW_FEAT_ASP GENMASK(29, 28)
197#define GMAC_HW_FEAT_FRPES GENMASK(14, 13)
198#define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)
199#define GMAC_HW_FEAT_FRPSEL BIT(10)
198
199/* MAC HW ADDR regs */
200#define GMAC_HI_DCS GENMASK(18, 16)
201#define GMAC_HI_DCS_SHIFT 16
202#define GMAC_HI_REG_AE BIT(31)
203
204/* MTL registers */
205#define MTL_OPERATION_MODE 0x00000c00
200
201/* MAC HW ADDR regs */
202#define GMAC_HI_DCS GENMASK(18, 16)
203#define GMAC_HI_DCS_SHIFT 16
204#define GMAC_HI_REG_AE BIT(31)
205
206/* MTL registers */
207#define MTL_OPERATION_MODE 0x00000c00
208#define MTL_FRPE BIT(15)
206#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
207#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
208#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
209#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
210#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
211#define MTL_OPERATION_RAA BIT(2)
212#define MTL_OPERATION_RAA_SP (0x0 << 2)
213#define MTL_OPERATION_RAA_WSP (0x1 << 2)

--- 191 unchanged lines hidden --- 		209#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
210#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
211#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
212#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
213#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
214#define MTL_OPERATION_RAA BIT(2)
215#define MTL_OPERATION_RAA_SP (0x0 << 2)
216#define MTL_OPERATION_RAA_WSP (0x1 << 2)

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