ocelot.c (c1bd8a2b9fbc304995fb03356f878579e50d3dd8) ocelot.c (d8ea7ff3995ead5193313c72c0d97c9c16c83be9)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <linux/dsa/ocelot.h>
7#include <linux/if_bridge.h>
8#include <soc/mscc/ocelot_vcap.h>
9#include "ocelot.h"
10#include "ocelot_vcap.h"
11
12#define TABLE_UPDATE_SLEEP_US 10
13#define TABLE_UPDATE_TIMEOUT_US 100000
14

--- 201 unchanged lines hidden (view full) ---

216
217 ocelot_rmw_gix(ocelot, val,
218 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
219 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
220 ANA_PORT_DROP_CFG, port);
221}
222
223int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
8#include <linux/if_bridge.h>
9#include <soc/mscc/ocelot_vcap.h>
10#include "ocelot.h"
11#include "ocelot_vcap.h"
12
13#define TABLE_UPDATE_SLEEP_US 10
14#define TABLE_UPDATE_TIMEOUT_US 100000
15

--- 201 unchanged lines hidden (view full) ---

217
218 ocelot_rmw_gix(ocelot, val,
219 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
220 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
221 ANA_PORT_DROP_CFG, port);
222}
223
224int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
224 bool vlan_aware, struct switchdev_trans *trans)
225 bool vlan_aware)
225{
226{
227 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
226 struct ocelot_port *ocelot_port = ocelot->ports[port];
228 struct ocelot_port *ocelot_port = ocelot->ports[port];
229 struct ocelot_vcap_filter *filter;
227 u32 val;
228
230 u32 val;
231
229 if (switchdev_trans_ph_prepare(trans)) {
230 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
231 struct ocelot_vcap_filter *filter;
232
233 list_for_each_entry(filter, &block->rules, list) {
234 if (filter->ingress_port_mask & BIT(port) &&
235 filter->action.vid_replace_ena) {
236 dev_err(ocelot->dev,
237 "Cannot change VLAN state with vlan modify rules active\n");
238 return -EBUSY;
239 }
232 list_for_each_entry(filter, &block->rules, list) {
233 if (filter->ingress_port_mask & BIT(port) &&
234 filter->action.vid_replace_ena) {
235 dev_err(ocelot->dev,
236 "Cannot change VLAN state with vlan modify rules active\n");
237 return -EBUSY;
240 }
238 }
241
242 return 0;
243 }
244
245 ocelot_port->vlan_aware = vlan_aware;
246
247 if (vlan_aware)
248 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
249 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
250 else

--- 377 unchanged lines hidden (view full) ---

628 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
629
630 /* Next ts */
631 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
632 }
633}
634EXPORT_SYMBOL(ocelot_get_txtstamp);
635
239 }
240
241 ocelot_port->vlan_aware = vlan_aware;
242
243 if (vlan_aware)
244 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
245 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
246 else

--- 377 unchanged lines hidden (view full) ---

624 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
625
626 /* Next ts */
627 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
628 }
629}
630EXPORT_SYMBOL(ocelot_get_txtstamp);
631
632static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
633 u32 *rval)
634{
635 u32 bytes_valid, val;
636
637 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
638 if (val == XTR_NOT_READY) {
639 if (ifh)
640 return -EIO;
641
642 do {
643 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
644 } while (val == XTR_NOT_READY);
645 }
646
647 switch (val) {
648 case XTR_ABORT:
649 return -EIO;
650 case XTR_EOF_0:
651 case XTR_EOF_1:
652 case XTR_EOF_2:
653 case XTR_EOF_3:
654 case XTR_PRUNED:
655 bytes_valid = XTR_VALID_BYTES(val);
656 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
657 if (val == XTR_ESCAPE)
658 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
659 else
660 *rval = val;
661
662 return bytes_valid;
663 case XTR_ESCAPE:
664 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
665
666 return 4;
667 default:
668 *rval = val;
669
670 return 4;
671 }
672}
673
674static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
675{
676 int i, err = 0;
677
678 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
679 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
680 if (err != 4)
681 return (err < 0) ? err : -EIO;
682 }
683
684 return 0;
685}
686
687int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
688{
689 struct skb_shared_hwtstamps *shhwtstamps;
690 u64 tod_in_ns, full_ts_in_ns, cpuq;
691 u64 timestamp, src_port, len;
692 u32 xfh[OCELOT_TAG_LEN / 4];
693 struct net_device *dev;
694 struct timespec64 ts;
695 struct sk_buff *skb;
696 int sz, buf_len;
697 u32 val, *buf;
698 int err;
699
700 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
701 if (err)
702 return err;
703
704 ocelot_xfh_get_src_port(xfh, &src_port);
705 ocelot_xfh_get_len(xfh, &len);
706 ocelot_xfh_get_rew_val(xfh, &timestamp);
707 ocelot_xfh_get_cpuq(xfh, &cpuq);
708
709 if (WARN_ON(src_port >= ocelot->num_phys_ports))
710 return -EINVAL;
711
712 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
713 if (!dev)
714 return -EINVAL;
715
716 skb = netdev_alloc_skb(dev, len);
717 if (unlikely(!skb)) {
718 netdev_err(dev, "Unable to allocate sk_buff\n");
719 return -ENOMEM;
720 }
721
722 buf_len = len - ETH_FCS_LEN;
723 buf = (u32 *)skb_put(skb, buf_len);
724
725 len = 0;
726 do {
727 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
728 if (sz < 0) {
729 err = sz;
730 goto out_free_skb;
731 }
732 *buf++ = val;
733 len += sz;
734 } while (len < buf_len);
735
736 /* Read the FCS */
737 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
738 if (sz < 0) {
739 err = sz;
740 goto out_free_skb;
741 }
742
743 /* Update the statistics if part of the FCS was read before */
744 len -= ETH_FCS_LEN - sz;
745
746 if (unlikely(dev->features & NETIF_F_RXFCS)) {
747 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
748 *buf = val;
749 }
750
751 if (ocelot->ptp) {
752 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
753
754 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
755 if ((tod_in_ns & 0xffffffff) < timestamp)
756 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
757 timestamp;
758 else
759 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
760 timestamp;
761
762 shhwtstamps = skb_hwtstamps(skb);
763 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
764 shhwtstamps->hwtstamp = full_ts_in_ns;
765 }
766
767 /* Everything we see on an interface that is in the HW bridge
768 * has already been forwarded.
769 */
770 if (ocelot->bridge_mask & BIT(src_port))
771 skb->offload_fwd_mark = 1;
772
773 skb->protocol = eth_type_trans(skb, dev);
774
775#if IS_ENABLED(CONFIG_BRIDGE_MRP)
776 if (skb->protocol == cpu_to_be16(ETH_P_MRP) &&
777 cpuq & BIT(OCELOT_MRP_CPUQ))
778 skb->offload_fwd_mark = 0;
779#endif
780
781 *nskb = skb;
782
783 return 0;
784
785out_free_skb:
786 kfree_skb(skb);
787 return err;
788}
789EXPORT_SYMBOL(ocelot_xtr_poll_frame);
790
791bool ocelot_can_inject(struct ocelot *ocelot, int grp)
792{
793 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
794
795 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
796 return false;
797 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
798 return false;
799
800 return true;
801}
802EXPORT_SYMBOL(ocelot_can_inject);
803
804void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
805 u32 rew_op, struct sk_buff *skb)
806{
807 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
808 unsigned int i, count, last;
809
810 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
811 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
812
813 ocelot_ifh_set_bypass(ifh, 1);
814 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
815 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
816 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb));
817 ocelot_ifh_set_rew_op(ifh, rew_op);
818
819 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
820 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
821
822 count = DIV_ROUND_UP(skb->len, 4);
823 last = skb->len % 4;
824 for (i = 0; i < count; i++)
825 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
826
827 /* Add padding */
828 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
829 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
830 i++;
831 }
832
833 /* Indicate EOF and valid bytes in last word */
834 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
835 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
836 QS_INJ_CTRL_EOF,
837 QS_INJ_CTRL, grp);
838
839 /* Add dummy CRC */
840 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
841 skb_tx_timestamp(skb);
842
843 skb->dev->stats.tx_packets++;
844 skb->dev->stats.tx_bytes += skb->len;
845}
846EXPORT_SYMBOL(ocelot_port_inject_frame);
847
848void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
849{
850 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
851 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
852}
853EXPORT_SYMBOL(ocelot_drain_cpu_queue);
854
636int ocelot_fdb_add(struct ocelot *ocelot, int port,
637 const unsigned char *addr, u16 vid)
638{
639 int pgid = port;
640
641 if (port == ocelot->npi)
642 pgid = PGID_CPU;
643

--- 299 unchanged lines hidden (view full) ---

943 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
944 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
945 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
946
947 return 0;
948}
949EXPORT_SYMBOL(ocelot_get_ts_info);
950
855int ocelot_fdb_add(struct ocelot *ocelot, int port,
856 const unsigned char *addr, u16 vid)
857{
858 int pgid = port;
859
860 if (port == ocelot->npi)
861 pgid = PGID_CPU;
862

--- 299 unchanged lines hidden (view full) ---

1162 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1163 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1164 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1165
1166 return 0;
1167}
1168EXPORT_SYMBOL(ocelot_get_ts_info);
1169
1170static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond,
1171 bool only_active_ports)
1172{
1173 u32 mask = 0;
1174 int port;
1175
1176 for (port = 0; port < ocelot->num_phys_ports; port++) {
1177 struct ocelot_port *ocelot_port = ocelot->ports[port];
1178
1179 if (!ocelot_port)
1180 continue;
1181
1182 if (ocelot_port->bond == bond) {
1183 if (only_active_ports && !ocelot_port->lag_tx_active)
1184 continue;
1185
1186 mask |= BIT(port);
1187 }
1188 }
1189
1190 return mask;
1191}
1192
1193static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
1194{
1195 u32 mask = 0;
1196 int port;
1197
1198 for (port = 0; port < ocelot->num_phys_ports; port++) {
1199 struct ocelot_port *ocelot_port = ocelot->ports[port];
1200
1201 if (!ocelot_port)
1202 continue;
1203
1204 if (ocelot_port->is_dsa_8021q_cpu)
1205 mask |= BIT(port);
1206 }
1207
1208 return mask;
1209}
1210
1211void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot)
1212{
1213 unsigned long cpu_fwd_mask;
1214 int port;
1215
1216 /* If a DSA tag_8021q CPU exists, it needs to be included in the
1217 * regular forwarding path of the front ports regardless of whether
1218 * those are bridged or standalone.
1219 * If DSA tag_8021q is not used, this returns 0, which is fine because
1220 * the hardware-based CPU port module can be a destination for packets
1221 * even if it isn't part of PGID_SRC.
1222 */
1223 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
1224
1225 /* Apply FWD mask. The loop is needed to add/remove the current port as
1226 * a source for the other ports.
1227 */
1228 for (port = 0; port < ocelot->num_phys_ports; port++) {
1229 struct ocelot_port *ocelot_port = ocelot->ports[port];
1230 unsigned long mask;
1231
1232 if (!ocelot_port) {
1233 /* Unused ports can't send anywhere */
1234 mask = 0;
1235 } else if (ocelot_port->is_dsa_8021q_cpu) {
1236 /* The DSA tag_8021q CPU ports need to be able to
1237 * forward packets to all other ports except for
1238 * themselves
1239 */
1240 mask = GENMASK(ocelot->num_phys_ports - 1, 0);
1241 mask &= ~cpu_fwd_mask;
1242 } else if (ocelot->bridge_fwd_mask & BIT(port)) {
1243 struct net_device *bond = ocelot_port->bond;
1244
1245 mask = ocelot->bridge_fwd_mask & ~BIT(port);
1246 if (bond) {
1247 mask &= ~ocelot_get_bond_mask(ocelot, bond,
1248 false);
1249 }
1250 } else {
1251 /* Standalone ports forward only to DSA tag_8021q CPU
1252 * ports (if those exist), or to the hardware CPU port
1253 * module otherwise.
1254 */
1255 mask = cpu_fwd_mask;
1256 }
1257
1258 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1259 }
1260}
1261EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
1262
951void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
952{
1263void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1264{
1265 struct ocelot_port *ocelot_port = ocelot->ports[port];
953 u32 port_cfg;
1266 u32 port_cfg;
954 int p, i;
955
956 if (!(BIT(port) & ocelot->bridge_mask))
957 return;
958
959 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
960
961 switch (state) {
962 case BR_STATE_FORWARDING:
963 ocelot->bridge_fwd_mask |= BIT(port);
964 fallthrough;
965 case BR_STATE_LEARNING:
1267
1268 if (!(BIT(port) & ocelot->bridge_mask))
1269 return;
1270
1271 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1272
1273 switch (state) {
1274 case BR_STATE_FORWARDING:
1275 ocelot->bridge_fwd_mask |= BIT(port);
1276 fallthrough;
1277 case BR_STATE_LEARNING:
966 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
1278 if (ocelot_port->learn_ena)
1279 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA;
967 break;
968
969 default:
970 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
971 ocelot->bridge_fwd_mask &= ~BIT(port);
972 break;
973 }
974
975 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
976
1280 break;
1281
1282 default:
1283 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA;
1284 ocelot->bridge_fwd_mask &= ~BIT(port);
1285 break;
1286 }
1287
1288 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port);
1289
977 /* Apply FWD mask. The loop is needed to add/remove the current port as
978 * a source for the other ports.
979 */
980 for (p = 0; p < ocelot->num_phys_ports; p++) {
981 if (ocelot->bridge_fwd_mask & BIT(p)) {
982 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p);
983
984 for (i = 0; i < ocelot->num_phys_ports; i++) {
985 unsigned long bond_mask = ocelot->lags[i];
986
987 if (!bond_mask)
988 continue;
989
990 if (bond_mask & BIT(p)) {
991 mask &= ~bond_mask;
992 break;
993 }
994 }
995
996 ocelot_write_rix(ocelot, mask,
997 ANA_PGID_PGID, PGID_SRC + p);
998 } else {
999 ocelot_write_rix(ocelot, 0,
1000 ANA_PGID_PGID, PGID_SRC + p);
1001 }
1002 }
1290 ocelot_apply_bridge_fwd_mask(ocelot);
1003}
1004EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1005
1006void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1007{
1008 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1009
1010 /* Setting AGE_PERIOD to zero effectively disables automatic aging,

--- 230 unchanged lines hidden (view full) ---

1241 return 0;
1242}
1243EXPORT_SYMBOL(ocelot_port_bridge_join);
1244
1245int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1246 struct net_device *bridge)
1247{
1248 struct ocelot_vlan pvid = {0}, native_vlan = {0};
1291}
1292EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1293
1294void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1295{
1296 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1297
1298 /* Setting AGE_PERIOD to zero effectively disables automatic aging,

--- 230 unchanged lines hidden (view full) ---

1529 return 0;
1530}
1531EXPORT_SYMBOL(ocelot_port_bridge_join);
1532
1533int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1534 struct net_device *bridge)
1535{
1536 struct ocelot_vlan pvid = {0}, native_vlan = {0};
1249 struct switchdev_trans trans;
1250 int ret;
1251
1252 ocelot->bridge_mask &= ~BIT(port);
1253
1254 if (!ocelot->bridge_mask)
1255 ocelot->hw_bridge_dev = NULL;
1256
1537 int ret;
1538
1539 ocelot->bridge_mask &= ~BIT(port);
1540
1541 if (!ocelot->bridge_mask)
1542 ocelot->hw_bridge_dev = NULL;
1543
1257 trans.ph_prepare = true;
1258 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans);
1544 ret = ocelot_port_vlan_filtering(ocelot, port, false);
1259 if (ret)
1260 return ret;
1261
1545 if (ret)
1546 return ret;
1547
1262 trans.ph_prepare = false;
1263 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans);
1264 if (ret)
1265 return ret;
1266
1267 ocelot_port_set_pvid(ocelot, port, pvid);
1268 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
1269
1270 return 0;
1271}
1272EXPORT_SYMBOL(ocelot_port_bridge_leave);
1273
1274static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1275{
1548 ocelot_port_set_pvid(ocelot, port, pvid);
1549 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
1550
1551 return 0;
1552}
1553EXPORT_SYMBOL(ocelot_port_bridge_leave);
1554
1555static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1556{
1557 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
1276 int i, port, lag;
1277
1278 /* Reset destination and aggregation PGIDS */
1279 for_each_unicast_dest_pgid(ocelot, port)
1280 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1281
1282 for_each_aggr_pgid(ocelot, i)
1283 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1284 ANA_PGID_PGID, i);
1285
1558 int i, port, lag;
1559
1560 /* Reset destination and aggregation PGIDS */
1561 for_each_unicast_dest_pgid(ocelot, port)
1562 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1563
1564 for_each_aggr_pgid(ocelot, i)
1565 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1566 ANA_PGID_PGID, i);
1567
1286 /* Now, set PGIDs for each LAG */
1568 /* The visited ports bitmask holds the list of ports offloading any
1569 * bonding interface. Initially we mark all these ports as unvisited,
1570 * then every time we visit a port in this bitmask, we know that it is
1571 * the lowest numbered port, i.e. the one whose logical ID == physical
1572 * port ID == LAG ID. So we mark as visited all further ports in the
1573 * bitmask that are offloading the same bonding interface. This way,
1574 * we set up the aggregation PGIDs only once per bonding interface.
1575 */
1576 for (port = 0; port < ocelot->num_phys_ports; port++) {
1577 struct ocelot_port *ocelot_port = ocelot->ports[port];
1578
1579 if (!ocelot_port || !ocelot_port->bond)
1580 continue;
1581
1582 visited &= ~BIT(port);
1583 }
1584
1585 /* Now, set PGIDs for each active LAG */
1287 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1586 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1587 struct net_device *bond = ocelot->ports[lag]->bond;
1588 int num_active_ports = 0;
1288 unsigned long bond_mask;
1589 unsigned long bond_mask;
1289 int aggr_count = 0;
1290 u8 aggr_idx[16];
1291
1590 u8 aggr_idx[16];
1591
1292 bond_mask = ocelot->lags[lag];
1293 if (!bond_mask)
1592 if (!bond || (visited & BIT(lag)))
1294 continue;
1295
1593 continue;
1594
1595 bond_mask = ocelot_get_bond_mask(ocelot, bond, true);
1596
1296 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1297 // Destination mask
1298 ocelot_write_rix(ocelot, bond_mask,
1299 ANA_PGID_PGID, port);
1597 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1598 // Destination mask
1599 ocelot_write_rix(ocelot, bond_mask,
1600 ANA_PGID_PGID, port);
1300 aggr_idx[aggr_count] = port;
1301 aggr_count++;
1601 aggr_idx[num_active_ports++] = port;
1302 }
1303
1304 for_each_aggr_pgid(ocelot, i) {
1305 u32 ac;
1306
1307 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1308 ac &= ~bond_mask;
1602 }
1603
1604 for_each_aggr_pgid(ocelot, i) {
1605 u32 ac;
1606
1607 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1608 ac &= ~bond_mask;
1309 ac |= BIT(aggr_idx[i % aggr_count]);
1609 /* Don't do division by zero if there was no active
1610 * port. Just make all aggregation codes zero.
1611 */
1612 if (num_active_ports)
1613 ac |= BIT(aggr_idx[i % num_active_ports]);
1310 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1311 }
1614 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1615 }
1312 }
1313}
1314
1616
1315static void ocelot_setup_lag(struct ocelot *ocelot, int lag)
1316{
1317 unsigned long bond_mask = ocelot->lags[lag];
1318 unsigned int p;
1617 /* Mark all ports in the same LAG as visited to avoid applying
1618 * the same config again.
1619 */
1620 for (port = lag; port < ocelot->num_phys_ports; port++) {
1621 struct ocelot_port *ocelot_port = ocelot->ports[port];
1319
1622
1320 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) {
1321 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p);
1623 if (!ocelot_port)
1624 continue;
1322
1625
1323 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1324
1325 /* Use lag port as logical port for port i */
1326 ocelot_write_gix(ocelot, port_cfg |
1327 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1328 ANA_PORT_PORT_CFG, p);
1626 if (ocelot_port->bond == bond)
1627 visited |= BIT(port);
1628 }
1329 }
1330}
1331
1629 }
1630}
1631
1332int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1333 struct net_device *bond)
1632/* When offloading a bonding interface, the switch ports configured under the
1633 * same bond must have the same logical port ID, equal to the physical port ID
1634 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
1635 * bridged mode, each port has a logical port ID equal to its physical port ID.
1636 */
1637static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
1334{
1638{
1335 struct net_device *ndev;
1336 u32 bond_mask = 0;
1337 int lag, lp;
1639 int port;
1338
1640
1339 rcu_read_lock();
1340 for_each_netdev_in_bond_rcu(bond, ndev) {
1341 struct ocelot_port_private *priv = netdev_priv(ndev);
1641 for (port = 0; port < ocelot->num_phys_ports; port++) {
1642 struct ocelot_port *ocelot_port = ocelot->ports[port];
1643 struct net_device *bond;
1342
1644
1343 bond_mask |= BIT(priv->chip_port);
1344 }
1345 rcu_read_unlock();
1645 if (!ocelot_port)
1646 continue;
1346
1647
1347 lp = __ffs(bond_mask);
1648 bond = ocelot_port->bond;
1649 if (bond) {
1650 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond,
1651 false));
1348
1652
1349 /* If the new port is the lowest one, use it as the logical port from
1350 * now on
1351 */
1352 if (port == lp) {
1353 lag = port;
1354 ocelot->lags[port] = bond_mask;
1355 bond_mask &= ~BIT(port);
1356 if (bond_mask) {
1357 lp = __ffs(bond_mask);
1358 ocelot->lags[lp] = 0;
1653 ocelot_rmw_gix(ocelot,
1654 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1655 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1656 ANA_PORT_PORT_CFG, port);
1657 } else {
1658 ocelot_rmw_gix(ocelot,
1659 ANA_PORT_PORT_CFG_PORTID_VAL(port),
1660 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1661 ANA_PORT_PORT_CFG, port);
1359 }
1662 }
1360 } else {
1361 lag = lp;
1362 ocelot->lags[lp] |= BIT(port);
1363 }
1663 }
1664}
1364
1665
1365 ocelot_setup_lag(ocelot, lag);
1666int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1667 struct net_device *bond,
1668 struct netdev_lag_upper_info *info)
1669{
1670 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
1671 return -EOPNOTSUPP;
1672
1673 ocelot->ports[port]->bond = bond;
1674
1675 ocelot_setup_logical_port_ids(ocelot);
1676 ocelot_apply_bridge_fwd_mask(ocelot);
1366 ocelot_set_aggr_pgids(ocelot);
1367
1368 return 0;
1369}
1370EXPORT_SYMBOL(ocelot_port_lag_join);
1371
1372void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1373 struct net_device *bond)
1374{
1677 ocelot_set_aggr_pgids(ocelot);
1678
1679 return 0;
1680}
1681EXPORT_SYMBOL(ocelot_port_lag_join);
1682
1683void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1684 struct net_device *bond)
1685{
1375 u32 port_cfg;
1376 int i;
1686 ocelot->ports[port]->bond = NULL;
1377
1687
1378 /* Remove port from any lag */
1379 for (i = 0; i < ocelot->num_phys_ports; i++)
1380 ocelot->lags[i] &= ~BIT(port);
1688 ocelot_setup_logical_port_ids(ocelot);
1689 ocelot_apply_bridge_fwd_mask(ocelot);
1690 ocelot_set_aggr_pgids(ocelot);
1691}
1692EXPORT_SYMBOL(ocelot_port_lag_leave);
1381
1693
1382 /* if it was the logical port of the lag, move the lag config to the
1383 * next port
1384 */
1385 if (ocelot->lags[port]) {
1386 int n = __ffs(ocelot->lags[port]);
1694void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
1695{
1696 struct ocelot_port *ocelot_port = ocelot->ports[port];
1387
1697
1388 ocelot->lags[n] = ocelot->lags[port];
1389 ocelot->lags[port] = 0;
1698 ocelot_port->lag_tx_active = lag_tx_active;
1390
1699
1391 ocelot_setup_lag(ocelot, n);
1392 }
1393
1394 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port);
1395 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M;
1396 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port),
1397 ANA_PORT_PORT_CFG, port);
1398
1700 /* Rebalance the LAGs */
1399 ocelot_set_aggr_pgids(ocelot);
1400}
1701 ocelot_set_aggr_pgids(ocelot);
1702}
1401EXPORT_SYMBOL(ocelot_port_lag_leave);
1703EXPORT_SYMBOL(ocelot_port_lag_change);
1402
1403/* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1404 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1405 * In the special case that it's the NPI port that we're configuring, the
1406 * length of the tag and optional prefix needs to be accounted for privately,
1407 * in order to be able to sustain communication at the requested @sdu.
1408 */
1409void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
1410{
1411 struct ocelot_port *ocelot_port = ocelot->ports[port];
1412 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
1413 int pause_start, pause_stop;
1414 int atop, atop_tot;
1415
1416 if (port == ocelot->npi) {
1417 maxlen += OCELOT_TAG_LEN;
1418
1704
1705/* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1706 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1707 * In the special case that it's the NPI port that we're configuring, the
1708 * length of the tag and optional prefix needs to be accounted for privately,
1709 * in order to be able to sustain communication at the requested @sdu.
1710 */
1711void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
1712{
1713 struct ocelot_port *ocelot_port = ocelot->ports[port];
1714 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
1715 int pause_start, pause_stop;
1716 int atop, atop_tot;
1717
1718 if (port == ocelot->npi) {
1719 maxlen += OCELOT_TAG_LEN;
1720
1419 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1721 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1420 maxlen += OCELOT_SHORT_PREFIX_LEN;
1722 maxlen += OCELOT_SHORT_PREFIX_LEN;
1421 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
1723 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1422 maxlen += OCELOT_LONG_PREFIX_LEN;
1423 }
1424
1425 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
1426
1427 /* Set Pause watermark hysteresis */
1428 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
1429 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
1430 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
1431 pause_start);
1432 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
1433 pause_stop);
1434
1435 /* Tail dropping watermarks */
1724 maxlen += OCELOT_LONG_PREFIX_LEN;
1725 }
1726
1727 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
1728
1729 /* Set Pause watermark hysteresis */
1730 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
1731 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
1732 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
1733 pause_start);
1734 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
1735 pause_stop);
1736
1737 /* Tail dropping watermarks */
1436 atop_tot = (ocelot->shared_queue_sz - 9 * maxlen) /
1738 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
1437 OCELOT_BUFFER_CELL_SZ;
1438 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
1439 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
1440 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
1441}
1442EXPORT_SYMBOL(ocelot_port_set_maxlen);
1443
1444int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
1445{
1446 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
1447
1448 if (port == ocelot->npi) {
1449 max_mtu -= OCELOT_TAG_LEN;
1450
1739 OCELOT_BUFFER_CELL_SZ;
1740 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
1741 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
1742 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
1743}
1744EXPORT_SYMBOL(ocelot_port_set_maxlen);
1745
1746int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
1747{
1748 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
1749
1750 if (port == ocelot->npi) {
1751 max_mtu -= OCELOT_TAG_LEN;
1752
1451 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1753 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1452 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
1754 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
1453 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG)
1755 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1454 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1455 }
1456
1457 return max_mtu;
1458}
1459EXPORT_SYMBOL(ocelot_get_max_mtu);
1460
1756 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1757 }
1758
1759 return max_mtu;
1760}
1761EXPORT_SYMBOL(ocelot_get_max_mtu);
1762
1763static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
1764 bool enabled)
1765{
1766 struct ocelot_port *ocelot_port = ocelot->ports[port];
1767 u32 val = 0;
1768
1769 if (enabled)
1770 val = ANA_PORT_PORT_CFG_LEARN_ENA;
1771
1772 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
1773 ANA_PORT_PORT_CFG, port);
1774
1775 ocelot_port->learn_ena = enabled;
1776}
1777
1778static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
1779 bool enabled)
1780{
1781 u32 val = 0;
1782
1783 if (enabled)
1784 val = BIT(port);
1785
1786 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
1787}
1788
1789static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
1790 bool enabled)
1791{
1792 u32 val = 0;
1793
1794 if (enabled)
1795 val = BIT(port);
1796
1797 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
1798}
1799
1800static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
1801 bool enabled)
1802{
1803 u32 val = 0;
1804
1805 if (enabled)
1806 val = BIT(port);
1807
1808 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
1809}
1810
1811int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
1812 struct switchdev_brport_flags flags)
1813{
1814 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1815 BR_BCAST_FLOOD))
1816 return -EINVAL;
1817
1818 return 0;
1819}
1820EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
1821
1822void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
1823 struct switchdev_brport_flags flags)
1824{
1825 if (flags.mask & BR_LEARNING)
1826 ocelot_port_set_learning(ocelot, port,
1827 !!(flags.val & BR_LEARNING));
1828
1829 if (flags.mask & BR_FLOOD)
1830 ocelot_port_set_ucast_flood(ocelot, port,
1831 !!(flags.val & BR_FLOOD));
1832
1833 if (flags.mask & BR_MCAST_FLOOD)
1834 ocelot_port_set_mcast_flood(ocelot, port,
1835 !!(flags.val & BR_MCAST_FLOOD));
1836
1837 if (flags.mask & BR_BCAST_FLOOD)
1838 ocelot_port_set_bcast_flood(ocelot, port,
1839 !!(flags.val & BR_BCAST_FLOOD));
1840}
1841EXPORT_SYMBOL(ocelot_port_bridge_flags);
1842
1461void ocelot_init_port(struct ocelot *ocelot, int port)
1462{
1463 struct ocelot_port *ocelot_port = ocelot->ports[port];
1464
1465 skb_queue_head_init(&ocelot_port->tx_skbs);
1466 spin_lock_init(&ocelot_port->ts_id_lock);
1467
1468 /* Basic L2 initialization */

--- 33 unchanged lines hidden (view full) ---

1502 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1503 ANA_PORT_DROP_CFG, port);
1504
1505 /* Set default VLAN and tag type to 8021Q. */
1506 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1507 REW_PORT_VLAN_CFG_PORT_TPID_M,
1508 REW_PORT_VLAN_CFG, port);
1509
1843void ocelot_init_port(struct ocelot *ocelot, int port)
1844{
1845 struct ocelot_port *ocelot_port = ocelot->ports[port];
1846
1847 skb_queue_head_init(&ocelot_port->tx_skbs);
1848 spin_lock_init(&ocelot_port->ts_id_lock);
1849
1850 /* Basic L2 initialization */

--- 33 unchanged lines hidden (view full) ---

1884 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1885 ANA_PORT_DROP_CFG, port);
1886
1887 /* Set default VLAN and tag type to 8021Q. */
1888 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1889 REW_PORT_VLAN_CFG_PORT_TPID_M,
1890 REW_PORT_VLAN_CFG, port);
1891
1892 /* Disable source address learning for standalone mode */
1893 ocelot_port_set_learning(ocelot, port, false);
1894
1510 /* Enable vcap lookups */
1511 ocelot_vcap_enable(ocelot, port);
1512}
1513EXPORT_SYMBOL(ocelot_init_port);
1514
1515/* Configure and enable the CPU port module, which is a set of queues
1516 * accessible through register MMIO, frame DMA or Ethernet (in case
1517 * NPI mode is used).

--- 12 unchanged lines hidden (view full) ---

1530 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1531 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1532 ANA_PORT_PORT_CFG, cpu);
1533
1534 /* Enable CPU port module */
1535 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1536 /* CPU port Injection/Extraction configuration */
1537 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
1895 /* Enable vcap lookups */
1896 ocelot_vcap_enable(ocelot, port);
1897}
1898EXPORT_SYMBOL(ocelot_init_port);
1899
1900/* Configure and enable the CPU port module, which is a set of queues
1901 * accessible through register MMIO, frame DMA or Ethernet (in case
1902 * NPI mode is used).

--- 12 unchanged lines hidden (view full) ---

1915 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
1916 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
1917 ANA_PORT_PORT_CFG, cpu);
1918
1919 /* Enable CPU port module */
1920 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
1921 /* CPU port Injection/Extraction configuration */
1922 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
1538 ocelot->xtr_prefix);
1923 OCELOT_TAG_PREFIX_NONE);
1539 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
1924 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
1540 ocelot->inj_prefix);
1925 OCELOT_TAG_PREFIX_NONE);
1541
1542 /* Configure the CPU port to be VLAN aware */
1543 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
1544 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
1545 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
1546 ANA_PORT_VLAN_CFG, cpu);
1547}
1548
1926
1927 /* Configure the CPU port to be VLAN aware */
1928 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
1929 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
1930 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
1931 ANA_PORT_VLAN_CFG, cpu);
1932}
1933
1934static void ocelot_detect_features(struct ocelot *ocelot)
1935{
1936 int mmgt, eq_ctrl;
1937
1938 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
1939 * the number of 240-byte free memory words (aka 4-cell chunks) and not
1940 * 192 bytes as the documentation incorrectly says.
1941 */
1942 mmgt = ocelot_read(ocelot, SYS_MMGT);
1943 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
1944
1945 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
1946 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
1947}
1948
1549int ocelot_init(struct ocelot *ocelot)
1550{
1551 char queue_name[32];
1552 int i, ret;
1553 u32 port;
1554
1555 if (ocelot->ops->reset) {
1556 ret = ocelot->ops->reset(ocelot);
1557 if (ret) {
1558 dev_err(ocelot->dev, "Switch reset failed\n");
1559 return ret;
1560 }
1561 }
1562
1949int ocelot_init(struct ocelot *ocelot)
1950{
1951 char queue_name[32];
1952 int i, ret;
1953 u32 port;
1954
1955 if (ocelot->ops->reset) {
1956 ret = ocelot->ops->reset(ocelot);
1957 if (ret) {
1958 dev_err(ocelot->dev, "Switch reset failed\n");
1959 return ret;
1960 }
1961 }
1962
1563 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports,
1564 sizeof(u32), GFP_KERNEL);
1565 if (!ocelot->lags)
1566 return -ENOMEM;
1567
1568 ocelot->stats = devm_kcalloc(ocelot->dev,
1569 ocelot->num_phys_ports * ocelot->num_stats,
1570 sizeof(u64), GFP_KERNEL);
1571 if (!ocelot->stats)
1572 return -ENOMEM;
1573
1574 mutex_init(&ocelot->stats_lock);
1575 mutex_init(&ocelot->ptp_lock);

--- 7 unchanged lines hidden (view full) ---

1583 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
1584 if (!ocelot->owq) {
1585 destroy_workqueue(ocelot->stats_queue);
1586 return -ENOMEM;
1587 }
1588
1589 INIT_LIST_HEAD(&ocelot->multicast);
1590 INIT_LIST_HEAD(&ocelot->pgids);
1963 ocelot->stats = devm_kcalloc(ocelot->dev,
1964 ocelot->num_phys_ports * ocelot->num_stats,
1965 sizeof(u64), GFP_KERNEL);
1966 if (!ocelot->stats)
1967 return -ENOMEM;
1968
1969 mutex_init(&ocelot->stats_lock);
1970 mutex_init(&ocelot->ptp_lock);

--- 7 unchanged lines hidden (view full) ---

1978 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
1979 if (!ocelot->owq) {
1980 destroy_workqueue(ocelot->stats_queue);
1981 return -ENOMEM;
1982 }
1983
1984 INIT_LIST_HEAD(&ocelot->multicast);
1985 INIT_LIST_HEAD(&ocelot->pgids);
1986 ocelot_detect_features(ocelot);
1591 ocelot_mact_init(ocelot);
1592 ocelot_vlan_init(ocelot);
1593 ocelot_vcap_init(ocelot);
1594 ocelot_cpu_port_init(ocelot);
1595
1596 for (port = 0; port < ocelot->num_phys_ports; port++) {
1597 /* Clear all counters (5 groups) */
1598 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1599 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1600 SYS_STAT_CFG);
1601 }
1602
1603 /* Only use S-Tag */
1604 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
1605
1606 /* Aggregation mode */
1607 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
1608 ANA_AGGR_CFG_AC_DMAC_ENA |
1609 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1987 ocelot_mact_init(ocelot);
1988 ocelot_vlan_init(ocelot);
1989 ocelot_vcap_init(ocelot);
1990 ocelot_cpu_port_init(ocelot);
1991
1992 for (port = 0; port < ocelot->num_phys_ports; port++) {
1993 /* Clear all counters (5 groups) */
1994 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
1995 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
1996 SYS_STAT_CFG);
1997 }
1998
1999 /* Only use S-Tag */
2000 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2001
2002 /* Aggregation mode */
2003 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2004 ANA_AGGR_CFG_AC_DMAC_ENA |
2005 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
1610 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG);
2006 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2007 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2008 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2009 ANA_AGGR_CFG);
1611
1612 /* Set MAC age time to default value. The entry is aged after
1613 * 2*AGE_PERIOD
1614 */
1615 ocelot_write(ocelot,
1616 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
1617 ANA_AUTOAGE);
1618
1619 /* Disable learning for frames discarded by VLAN ingress filtering */
1620 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
1621
1622 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
1623 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
1624 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
1625
1626 /* Setup flooding PGIDs */
1627 for (i = 0; i < ocelot->num_flooding_pgids; i++)
1628 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2010
2011 /* Set MAC age time to default value. The entry is aged after
2012 * 2*AGE_PERIOD
2013 */
2014 ocelot_write(ocelot,
2015 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2016 ANA_AUTOAGE);
2017
2018 /* Disable learning for frames discarded by VLAN ingress filtering */
2019 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2020
2021 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2022 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2023 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2024
2025 /* Setup flooding PGIDs */
2026 for (i = 0; i < ocelot->num_flooding_pgids; i++)
2027 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
1629 ANA_FLOODING_FLD_BROADCAST(PGID_MC) |
2028 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
1630 ANA_FLOODING_FLD_UNICAST(PGID_UC),
1631 ANA_FLOODING, i);
1632 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
1633 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
1634 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
1635 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
1636 ANA_FLOODING_IPMC);
1637

--- 4 unchanged lines hidden (view full) ---

1642 ocelot_write_gix(ocelot,
1643 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
1644 ANA_PORT_CPU_FWD_BPDU_CFG,
1645 port);
1646 /* Ensure bridging is disabled */
1647 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
1648 }
1649
2029 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2030 ANA_FLOODING, i);
2031 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2032 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2033 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2034 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2035 ANA_FLOODING_IPMC);
2036

--- 4 unchanged lines hidden (view full) ---

2041 ocelot_write_gix(ocelot,
2042 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2043 ANA_PORT_CPU_FWD_BPDU_CFG,
2044 port);
2045 /* Ensure bridging is disabled */
2046 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2047 }
2048
1650 /* Allow broadcast MAC frames. */
1651 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
1652 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
1653
1654 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
1655 }
2049 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
2050 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2051
2052 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2053 }
1656 ocelot_write_rix(ocelot,
1657 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
1658 ANA_PGID_PGID, PGID_MC);
2054 /* Allow broadcast and unknown L2 multicast to the CPU. */
2055 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2056 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2057 ANA_PGID_PGID, PGID_MC);
2058 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2059 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2060 ANA_PGID_PGID, PGID_BC);
1659 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
1660 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
1661
1662 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
1663 * registers endianness.
1664 */
1665 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
1666 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);

--- 42 unchanged lines hidden --- 		2061 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2062 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2063
2064 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2065 * registers endianness.
2066 */
2067 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2068 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);

--- 42 unchanged lines hidden ---