trap.h (eadcbfa58ae8693f0d6a0f591d8f51d55cf068e1) trap.h (0db7b386f5e779085d5e20ad9d88b8a4b8767c02)
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/trap.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
5 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

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61 MLXSW_TRAP_ID_MTUERROR = 0x52,
62 MLXSW_TRAP_ID_TTLERROR = 0x53,
63 MLXSW_TRAP_ID_LBERROR = 0x54,
64 MLXSW_TRAP_ID_OSPF = 0x55,
65 MLXSW_TRAP_ID_IP2ME = 0x5F,
66 MLXSW_TRAP_ID_RTR_INGRESS0 = 0x70,
67 MLXSW_TRAP_ID_BGP_IPV4 = 0x88,
68 MLXSW_TRAP_ID_HOST_MISS_IPV4 = 0x90,
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/trap.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
5 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 52 unchanged lines hidden (view full) ---

61 MLXSW_TRAP_ID_MTUERROR = 0x52,
62 MLXSW_TRAP_ID_TTLERROR = 0x53,
63 MLXSW_TRAP_ID_LBERROR = 0x54,
64 MLXSW_TRAP_ID_OSPF = 0x55,
65 MLXSW_TRAP_ID_IP2ME = 0x5F,
66 MLXSW_TRAP_ID_RTR_INGRESS0 = 0x70,
67 MLXSW_TRAP_ID_BGP_IPV4 = 0x88,
68 MLXSW_TRAP_ID_HOST_MISS_IPV4 = 0x90,
69 MLXSW_TRAP_ID_ACL0 = 0x1C0,
69
70 MLXSW_TRAP_ID_MAX = 0x1FF
71};
72
73enum mlxsw_event_trap_id {
74 /* Port Up/Down event generated by hardware */
75 MLXSW_TRAP_ID_PUDE = 0x8,
76};
77
78#endif /* _MLXSW_TRAP_H */
70
71 MLXSW_TRAP_ID_MAX = 0x1FF
72};
73
74enum mlxsw_event_trap_id {
75 /* Port Up/Down event generated by hardware */
76 MLXSW_TRAP_ID_PUDE = 0x8,
77};
78
79#endif /* _MLXSW_TRAP_H */