trap.h (cc9263874b42bf98209dce0afe698b550648e770) trap.h (c20b80187a93b4fcc1c5c46fc8a436df1f17636d)
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/trap.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
5 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

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51 MLXSW_TRAP_ID_DHCP = 0x19,
52 MLXSW_TRAP_ID_IGMP_QUERY = 0x30,
53 MLXSW_TRAP_ID_IGMP_V1_REPORT = 0x31,
54 MLXSW_TRAP_ID_IGMP_V2_REPORT = 0x32,
55 MLXSW_TRAP_ID_IGMP_V2_LEAVE = 0x33,
56 MLXSW_TRAP_ID_IGMP_V3_REPORT = 0x34,
57 MLXSW_TRAP_ID_ARPBC = 0x50,
58 MLXSW_TRAP_ID_ARPUC = 0x51,
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/trap.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
5 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 42 unchanged lines hidden (view full) ---

51 MLXSW_TRAP_ID_DHCP = 0x19,
52 MLXSW_TRAP_ID_IGMP_QUERY = 0x30,
53 MLXSW_TRAP_ID_IGMP_V1_REPORT = 0x31,
54 MLXSW_TRAP_ID_IGMP_V2_REPORT = 0x32,
55 MLXSW_TRAP_ID_IGMP_V2_LEAVE = 0x33,
56 MLXSW_TRAP_ID_IGMP_V3_REPORT = 0x34,
57 MLXSW_TRAP_ID_ARPBC = 0x50,
58 MLXSW_TRAP_ID_ARPUC = 0x51,
59 MLXSW_TRAP_ID_MTUERROR = 0x52,
60 MLXSW_TRAP_ID_TTLERROR = 0x53,
61 MLXSW_TRAP_ID_OSPF = 0x55,
59 MLXSW_TRAP_ID_IP2ME = 0x5F,
60 MLXSW_TRAP_ID_RTR_INGRESS0 = 0x70,
61 MLXSW_TRAP_ID_HOST_MISS_IPV4 = 0x90,
62
63 MLXSW_TRAP_ID_MAX = 0x1FF
64};
65
66enum mlxsw_event_trap_id {
67 /* Port Up/Down event generated by hardware */
68 MLXSW_TRAP_ID_PUDE = 0x8,
69};
70
71#endif /* _MLXSW_TRAP_H */
62 MLXSW_TRAP_ID_IP2ME = 0x5F,
63 MLXSW_TRAP_ID_RTR_INGRESS0 = 0x70,
64 MLXSW_TRAP_ID_HOST_MISS_IPV4 = 0x90,
65
66 MLXSW_TRAP_ID_MAX = 0x1FF
67};
68
69enum mlxsw_event_trap_id {
70 /* Port Up/Down event generated by hardware */
71 MLXSW_TRAP_ID_PUDE = 0x8,
72};
73
74#endif /* _MLXSW_TRAP_H */