spectrum.c (1222d15a01c7a3a76a5988df341998a647ff462c) spectrum.c (c3ab435466d5109b2c7525a3b90107d4d9e918fc)
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

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86 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
87};
88
89#define MLXSW_SP1_FW_FILENAME \
90 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
91 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
92 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
93
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 77 unchanged lines hidden (view full) ---

86 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
87};
88
89#define MLXSW_SP1_FW_FILENAME \
90 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
91 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
92 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
93
94static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
94static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
95static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
95static const char mlxsw_sp_driver_version[] = "1.0";
96
97/* tx_hdr_version
98 * Tx header version.
99 * Must be set to 1.
100 */
101MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
102

--- 1619 unchanged lines hidden (view full) ---

1722};
1723
1724static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1725 struct ethtool_drvinfo *drvinfo)
1726{
1727 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1728 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1729
96static const char mlxsw_sp_driver_version[] = "1.0";
97
98/* tx_hdr_version
99 * Tx header version.
100 * Must be set to 1.
101 */
102MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
103

--- 1619 unchanged lines hidden (view full) ---

1723};
1724
1725static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1726 struct ethtool_drvinfo *drvinfo)
1727{
1728 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1729 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1730
1730 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1731 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1732 sizeof(drvinfo->driver));
1731 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1732 sizeof(drvinfo->version));
1733 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1734 "%d.%d.%d",
1735 mlxsw_sp->bus_info->fw_rev.major,
1736 mlxsw_sp->bus_info->fw_rev.minor,
1737 mlxsw_sp->bus_info->fw_rev.subminor);
1738 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,

--- 1952 unchanged lines hidden (view full) ---

3691 unsigned long event, void *ptr);
3692
3693static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3694 const struct mlxsw_bus_info *mlxsw_bus_info)
3695{
3696 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3697 int err;
3698
1733 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1734 sizeof(drvinfo->version));
1735 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1736 "%d.%d.%d",
1737 mlxsw_sp->bus_info->fw_rev.major,
1738 mlxsw_sp->bus_info->fw_rev.minor,
1739 mlxsw_sp->bus_info->fw_rev.subminor);
1740 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,

--- 1952 unchanged lines hidden (view full) ---

3693 unsigned long event, void *ptr);
3694
3695static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3696 const struct mlxsw_bus_info *mlxsw_bus_info)
3697{
3698 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3699 int err;
3700
3699 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3700 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
3701 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3702 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3703 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3704 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3705 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3706
3707 mlxsw_sp->core = mlxsw_core;
3708 mlxsw_sp->bus_info = mlxsw_bus_info;
3709
3710 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3711 if (err) {
3712 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3713 return err;
3714 }

--- 122 unchanged lines hidden (view full) ---

3837 mlxsw_sp_traps_fini(mlxsw_sp);
3838err_traps_init:
3839 mlxsw_sp_fids_fini(mlxsw_sp);
3840err_fids_init:
3841 mlxsw_sp_kvdl_fini(mlxsw_sp);
3842 return err;
3843}
3844
3701 mlxsw_sp->core = mlxsw_core;
3702 mlxsw_sp->bus_info = mlxsw_bus_info;
3703
3704 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3705 if (err) {
3706 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3707 return err;
3708 }

--- 122 unchanged lines hidden (view full) ---

3831 mlxsw_sp_traps_fini(mlxsw_sp);
3832err_traps_init:
3833 mlxsw_sp_fids_fini(mlxsw_sp);
3834err_fids_init:
3835 mlxsw_sp_kvdl_fini(mlxsw_sp);
3836 return err;
3837}
3838
3839static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3840 const struct mlxsw_bus_info *mlxsw_bus_info)
3841{
3842 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3843
3844 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
3845 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
3846 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3847 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3848 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3849 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3850 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3851
3852 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3853}
3854
3855static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3856 const struct mlxsw_bus_info *mlxsw_bus_info)
3857{
3858 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3859
3860 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3861 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3862 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3863 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3864 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3865
3866 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
3867}
3868
3845static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3846{
3847 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3848
3849 mlxsw_sp_ports_remove(mlxsw_sp);
3850 mlxsw_sp_dpipe_fini(mlxsw_sp);
3851 mlxsw_sp_acl_fini(mlxsw_sp);
3852 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);

--- 4 unchanged lines hidden (view full) ---

3857 mlxsw_sp_span_fini(mlxsw_sp);
3858 mlxsw_sp_lag_fini(mlxsw_sp);
3859 mlxsw_sp_buffers_fini(mlxsw_sp);
3860 mlxsw_sp_traps_fini(mlxsw_sp);
3861 mlxsw_sp_fids_fini(mlxsw_sp);
3862 mlxsw_sp_kvdl_fini(mlxsw_sp);
3863}
3864
3869static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3870{
3871 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3872
3873 mlxsw_sp_ports_remove(mlxsw_sp);
3874 mlxsw_sp_dpipe_fini(mlxsw_sp);
3875 mlxsw_sp_acl_fini(mlxsw_sp);
3876 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);

--- 4 unchanged lines hidden (view full) ---

3881 mlxsw_sp_span_fini(mlxsw_sp);
3882 mlxsw_sp_lag_fini(mlxsw_sp);
3883 mlxsw_sp_buffers_fini(mlxsw_sp);
3884 mlxsw_sp_traps_fini(mlxsw_sp);
3885 mlxsw_sp_fids_fini(mlxsw_sp);
3886 mlxsw_sp_kvdl_fini(mlxsw_sp);
3887}
3888
3865static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
3889static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3866 .used_max_mid = 1,
3867 .max_mid = MLXSW_SP_MID_MAX,
3868 .used_flood_tables = 1,
3869 .used_flood_mode = 1,
3870 .flood_mode = 3,
3871 .max_fid_offset_flood_tables = 3,
3872 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3873 .max_fid_flood_tables = 3,

--- 9 unchanged lines hidden (view full) ---

3883 .swid_config = {
3884 {
3885 .used_type = 1,
3886 .type = MLXSW_PORT_SWID_TYPE_ETH,
3887 }
3888 },
3889};
3890
3890 .used_max_mid = 1,
3891 .max_mid = MLXSW_SP_MID_MAX,
3892 .used_flood_tables = 1,
3893 .used_flood_mode = 1,
3894 .flood_mode = 3,
3895 .max_fid_offset_flood_tables = 3,
3896 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3897 .max_fid_flood_tables = 3,

--- 9 unchanged lines hidden (view full) ---

3907 .swid_config = {
3908 {
3909 .used_type = 1,
3910 .type = MLXSW_PORT_SWID_TYPE_ETH,
3911 }
3912 },
3913};
3914
3915static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3916 .used_max_mid = 1,
3917 .max_mid = MLXSW_SP_MID_MAX,
3918 .used_flood_tables = 1,
3919 .used_flood_mode = 1,
3920 .flood_mode = 3,
3921 .max_fid_offset_flood_tables = 3,
3922 .fid_offset_flood_table_size = VLAN_N_VID - 1,
3923 .max_fid_flood_tables = 3,
3924 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
3925 .used_max_ib_mc = 1,
3926 .max_ib_mc = 0,
3927 .used_max_pkey = 1,
3928 .max_pkey = 0,
3929 .swid_config = {
3930 {
3931 .used_type = 1,
3932 .type = MLXSW_PORT_SWID_TYPE_ETH,
3933 }
3934 },
3935};
3936
3891static void
3892mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3893 struct devlink_resource_size_params *kvd_size_params,
3894 struct devlink_resource_size_params *linear_size_params,
3895 struct devlink_resource_size_params *hash_double_size_params,
3896 struct devlink_resource_size_params *hash_single_size_params)
3897{
3898 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,

--- 20 unchanged lines hidden (view full) ---

3919 devlink_resource_size_params_init(hash_single_size_params,
3920 single_size_min,
3921 kvd_size - double_size_min -
3922 linear_size_min,
3923 MLXSW_SP_KVD_GRANULARITY,
3924 DEVLINK_RESOURCE_UNIT_ENTRY);
3925}
3926
3937static void
3938mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3939 struct devlink_resource_size_params *kvd_size_params,
3940 struct devlink_resource_size_params *linear_size_params,
3941 struct devlink_resource_size_params *hash_double_size_params,
3942 struct devlink_resource_size_params *hash_single_size_params)
3943{
3944 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,

--- 20 unchanged lines hidden (view full) ---

3965 devlink_resource_size_params_init(hash_single_size_params,
3966 single_size_min,
3967 kvd_size - double_size_min -
3968 linear_size_min,
3969 MLXSW_SP_KVD_GRANULARITY,
3970 DEVLINK_RESOURCE_UNIT_ENTRY);
3971}
3972
3927static int mlxsw_sp_resources_register(struct mlxsw_core *mlxsw_core)
3973static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3928{
3929 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3930 struct devlink_resource_size_params hash_single_size_params;
3931 struct devlink_resource_size_params hash_double_size_params;
3932 struct devlink_resource_size_params linear_size_params;
3933 struct devlink_resource_size_params kvd_size_params;
3934 u32 kvd_size, single_size, double_size, linear_size;
3935 const struct mlxsw_config_profile *profile;
3936 int err;
3937
3974{
3975 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3976 struct devlink_resource_size_params hash_single_size_params;
3977 struct devlink_resource_size_params hash_double_size_params;
3978 struct devlink_resource_size_params linear_size_params;
3979 struct devlink_resource_size_params kvd_size_params;
3980 u32 kvd_size, single_size, double_size, linear_size;
3981 const struct mlxsw_config_profile *profile;
3982 int err;
3983
3938 profile = &mlxsw_sp_config_profile;
3984 profile = &mlxsw_sp1_config_profile;
3939 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3940 return -EIO;
3941
3942 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3943 &linear_size_params,
3944 &hash_double_size_params,
3945 &hash_single_size_params);
3946

--- 38 unchanged lines hidden (view full) ---

3985 MLXSW_SP_RESOURCE_KVD,
3986 &hash_single_size_params);
3987 if (err)
3988 return err;
3989
3990 return 0;
3991}
3992
3985 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3986 return -EIO;
3987
3988 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3989 &linear_size_params,
3990 &hash_double_size_params,
3991 &hash_single_size_params);
3992

--- 38 unchanged lines hidden (view full) ---

4031 MLXSW_SP_RESOURCE_KVD,
4032 &hash_single_size_params);
4033 if (err)
4034 return err;
4035
4036 return 0;
4037}
4038
4039static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
4040{
4041 return mlxsw_sp1_resources_kvd_register(mlxsw_core);
4042}
4043
4044static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
4045{
4046 return 0;
4047}
4048
3993static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3994 const struct mlxsw_config_profile *profile,
3995 u64 *p_single_size, u64 *p_double_size,
3996 u64 *p_linear_size)
3997{
3998 struct devlink *devlink = priv_to_devlink(mlxsw_core);
3999 u32 double_size;
4000 int err;

--- 39 unchanged lines hidden (view full) ---

4040 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4041 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4042 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4043 return -EIO;
4044
4045 return 0;
4046}
4047
4049static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
4050 const struct mlxsw_config_profile *profile,
4051 u64 *p_single_size, u64 *p_double_size,
4052 u64 *p_linear_size)
4053{
4054 struct devlink *devlink = priv_to_devlink(mlxsw_core);
4055 u32 double_size;
4056 int err;

--- 39 unchanged lines hidden (view full) ---

4096 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
4097 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
4098 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
4099 return -EIO;
4100
4101 return 0;
4102}
4103
4048static struct mlxsw_driver mlxsw_sp_driver = {
4049 .kind = mlxsw_sp_driver_name,
4104static struct mlxsw_driver mlxsw_sp1_driver = {
4105 .kind = mlxsw_sp1_driver_name,
4050 .priv_size = sizeof(struct mlxsw_sp),
4106 .priv_size = sizeof(struct mlxsw_sp),
4051 .init = mlxsw_sp_init,
4107 .init = mlxsw_sp1_init,
4052 .fini = mlxsw_sp_fini,
4053 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4054 .port_split = mlxsw_sp_port_split,
4055 .port_unsplit = mlxsw_sp_port_unsplit,
4056 .sb_pool_get = mlxsw_sp_sb_pool_get,
4057 .sb_pool_set = mlxsw_sp_sb_pool_set,
4058 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4059 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4060 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4061 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4062 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4063 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4064 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4065 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4066 .txhdr_construct = mlxsw_sp_txhdr_construct,
4108 .fini = mlxsw_sp_fini,
4109 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4110 .port_split = mlxsw_sp_port_split,
4111 .port_unsplit = mlxsw_sp_port_unsplit,
4112 .sb_pool_get = mlxsw_sp_sb_pool_get,
4113 .sb_pool_set = mlxsw_sp_sb_pool_set,
4114 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4115 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4116 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4117 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4118 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4119 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4120 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4121 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4122 .txhdr_construct = mlxsw_sp_txhdr_construct,
4067 .resources_register = mlxsw_sp_resources_register,
4123 .resources_register = mlxsw_sp1_resources_register,
4068 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
4069 .txhdr_len = MLXSW_TXHDR_LEN,
4124 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
4125 .txhdr_len = MLXSW_TXHDR_LEN,
4070 .profile = &mlxsw_sp_config_profile,
4126 .profile = &mlxsw_sp1_config_profile,
4071 .res_query_enabled = true,
4072};
4073
4127 .res_query_enabled = true,
4128};
4129
4130static struct mlxsw_driver mlxsw_sp2_driver = {
4131 .kind = mlxsw_sp2_driver_name,
4132 .priv_size = sizeof(struct mlxsw_sp),
4133 .init = mlxsw_sp2_init,
4134 .fini = mlxsw_sp_fini,
4135 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
4136 .port_split = mlxsw_sp_port_split,
4137 .port_unsplit = mlxsw_sp_port_unsplit,
4138 .sb_pool_get = mlxsw_sp_sb_pool_get,
4139 .sb_pool_set = mlxsw_sp_sb_pool_set,
4140 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4141 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4142 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4143 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4144 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4145 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4146 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4147 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4148 .txhdr_construct = mlxsw_sp_txhdr_construct,
4149 .resources_register = mlxsw_sp2_resources_register,
4150 .txhdr_len = MLXSW_TXHDR_LEN,
4151 .profile = &mlxsw_sp2_config_profile,
4152 .res_query_enabled = true,
4153};
4154
4074bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4075{
4076 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4077}
4078
4079static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
4080{
4081 struct mlxsw_sp_port **p_mlxsw_sp_port = data;

--- 759 unchanged lines hidden (view full) ---

4841static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4842 .notifier_call = mlxsw_sp_inet6addr_valid_event,
4843};
4844
4845static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4846 .notifier_call = mlxsw_sp_inet6addr_event,
4847};
4848
4155bool mlxsw_sp_port_dev_check(const struct net_device *dev)
4156{
4157 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4158}
4159
4160static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
4161{
4162 struct mlxsw_sp_port **p_mlxsw_sp_port = data;

--- 759 unchanged lines hidden (view full) ---

4922static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4923 .notifier_call = mlxsw_sp_inet6addr_valid_event,
4924};
4925
4926static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4927 .notifier_call = mlxsw_sp_inet6addr_event,
4928};
4929
4849static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4930static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
4850 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4851 {0, },
4852};
4853
4931 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4932 {0, },
4933};
4934
4854static struct pci_driver mlxsw_sp_pci_driver = {
4855 .name = mlxsw_sp_driver_name,
4856 .id_table = mlxsw_sp_pci_id_table,
4935static struct pci_driver mlxsw_sp1_pci_driver = {
4936 .name = mlxsw_sp1_driver_name,
4937 .id_table = mlxsw_sp1_pci_id_table,
4857};
4858
4938};
4939
4940static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
4941 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
4942 {0, },
4943};
4944
4945static struct pci_driver mlxsw_sp2_pci_driver = {
4946 .name = mlxsw_sp2_driver_name,
4947 .id_table = mlxsw_sp2_pci_id_table,
4948};
4949
4859static int __init mlxsw_sp_module_init(void)
4860{
4861 int err;
4862
4863 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4864 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4865 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4866 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4867
4950static int __init mlxsw_sp_module_init(void)
4951{
4952 int err;
4953
4954 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4955 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4956 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4957 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4958
4868 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4959 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
4869 if (err)
4960 if (err)
4870 goto err_core_driver_register;
4961 goto err_sp1_core_driver_register;
4871
4962
4872 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4963 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
4873 if (err)
4964 if (err)
4874 goto err_pci_driver_register;
4965 goto err_sp2_core_driver_register;
4875
4966
4967 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
4968 if (err)
4969 goto err_sp1_pci_driver_register;
4970
4971 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
4972 if (err)
4973 goto err_sp2_pci_driver_register;
4974
4876 return 0;
4877
4975 return 0;
4976
4878err_pci_driver_register:
4879 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4880err_core_driver_register:
4977err_sp2_pci_driver_register:
4978 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
4979err_sp1_pci_driver_register:
4980 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
4981err_sp2_core_driver_register:
4982 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
4983err_sp1_core_driver_register:
4881 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4882 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4883 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4884 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4885 return err;
4886}
4887
4888static void __exit mlxsw_sp_module_exit(void)
4889{
4984 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4985 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4986 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4987 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4988 return err;
4989}
4990
4991static void __exit mlxsw_sp_module_exit(void)
4992{
4890 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
4891 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
4993 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
4994 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
4995 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
4996 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
4892 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4893 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4894 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
4895 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
4896}
4897
4898module_init(mlxsw_sp_module_init);
4899module_exit(mlxsw_sp_module_exit);
4900
4901MODULE_LICENSE("Dual BSD/GPL");
4902MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4903MODULE_DESCRIPTION("Mellanox Spectrum driver");
4997 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
4998 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
4999 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
5000 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
5001}
5002
5003module_init(mlxsw_sp_module_init);
5004module_exit(mlxsw_sp_module_exit);
5005
5006MODULE_LICENSE("Dual BSD/GPL");
5007MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5008MODULE_DESCRIPTION("Mellanox Spectrum driver");
4904MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
5009MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5010MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
4905MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
5011MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);