port.h (4ec14b7634b298186f18f65d959354dc3c60e02c) port.h (31557f0f9755696530d08465cf9940404f2d48e2)
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/port.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
5 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

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46#define MLXSW_PORT_SWID_ALL_SWIDS 254
47#define MLXSW_PORT_SWID_TYPE_ETH 2
48
49#define MLXSW_PORT_MID 0xd000
50
51#define MLXSW_PORT_MAX_PHY_PORTS 0x40
52#define MLXSW_PORT_MAX_PORTS MLXSW_PORT_MAX_PHY_PORTS
53
1/*
2 * drivers/net/ethernet/mellanox/mlxsw/port.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
5 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
6 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 37 unchanged lines hidden (view full) ---

46#define MLXSW_PORT_SWID_ALL_SWIDS 254
47#define MLXSW_PORT_SWID_TYPE_ETH 2
48
49#define MLXSW_PORT_MID 0xd000
50
51#define MLXSW_PORT_MAX_PHY_PORTS 0x40
52#define MLXSW_PORT_MAX_PORTS MLXSW_PORT_MAX_PHY_PORTS
53
54#define MLXSW_PORT_DEVID_BITS_OFFSET 10
55#define MLXSW_PORT_PHY_BITS_OFFSET 4
56#define MLXSW_PORT_PHY_BITS_MASK (MLXSW_PORT_MAX_PHY_PORTS - 1)
57
54#define MLXSW_PORT_CPU_PORT 0x0
55
56#define MLXSW_PORT_DONT_CARE (MLXSW_PORT_MAX_PORTS)
57
58enum mlxsw_port_admin_status {
59 MLXSW_PORT_ADMIN_STATUS_UP = 1,
60 MLXSW_PORT_ADMIN_STATUS_DOWN = 2,
61 MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3,
62 MLXSW_PORT_ADMIN_STATUS_DISABLED = 4,
63};
64
65enum mlxsw_reg_pude_oper_status {
66 MLXSW_PORT_OPER_STATUS_UP = 1,
67 MLXSW_PORT_OPER_STATUS_DOWN = 2,
68 MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */
69};
70
71#endif /* _MLXSW_PORT_H */
58#define MLXSW_PORT_CPU_PORT 0x0
59
60#define MLXSW_PORT_DONT_CARE (MLXSW_PORT_MAX_PORTS)
61
62enum mlxsw_port_admin_status {
63 MLXSW_PORT_ADMIN_STATUS_UP = 1,
64 MLXSW_PORT_ADMIN_STATUS_DOWN = 2,
65 MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3,
66 MLXSW_PORT_ADMIN_STATUS_DISABLED = 4,
67};
68
69enum mlxsw_reg_pude_oper_status {
70 MLXSW_PORT_OPER_STATUS_UP = 1,
71 MLXSW_PORT_OPER_STATUS_DOWN = 2,
72 MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */
73};
74
75#endif /* _MLXSW_PORT_H */