fw.c (f53f292eeaa234615c31a1306babe703fc4263f2) fw.c (d998735f443427c1530cac5eeda0a45c8cb60a57)
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file

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86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file

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86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "DPDP",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
112 [59] = "Port management change event support",
113 [61] = "64 byte EQE support",
114 [62] = "64 byte CQE support",
115 };
116 int i;
117
118 mlx4_dbg(dev, "DEV_CAP flags:\n");
119 for (i = 0; i < ARRAY_SIZE(fname); ++i)
120 if (fname[i] && (flags & (1LL << i)))
121 mlx4_dbg(dev, " %s\n", fname[i]);
122}
123
124static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
125{
126 static const char * const fname[] = {
127 [0] = "RSS support",
128 [1] = "RSS Toeplitz Hash Function support",
129 [2] = "RSS XOR Hash Function support",
130 [3] = "Device manage flow steering support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device manage flow steering support",
131 [4] = "Automatic mac reassignment support"
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support"
132 };
133 int i;
134
135 for (i = 0; i < ARRAY_SIZE(fname); ++i)
136 if (fname[i] && (flags & (1LL << i)))
137 mlx4_dbg(dev, " %s\n", fname[i]);
138}
139

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437#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
438#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
439#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
440#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
441#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
442#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
443#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
444#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
135 };
136 int i;
137
138 for (i = 0; i < ARRAY_SIZE(fname); ++i)
139 if (fname[i] && (flags & (1LL << i)))
140 mlx4_dbg(dev, " %s\n", fname[i]);
141}
142

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440#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
441#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
442#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
443#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
444#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
445#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
446#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
447#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
448#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
445#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
446#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
447#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
448#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
449#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
450#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
451#define QUERY_DEV_CAP_BF_OFFSET 0x4c
452#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d

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553 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
554 if (field & 0x80)
555 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
556 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
557 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
558 dev_cap->fs_max_num_qp_per_entry = field;
559 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
560 dev_cap->stat_rate_support = stat_rate;
449#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
450#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
451#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
452#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
453#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
454#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
455#define QUERY_DEV_CAP_BF_OFFSET 0x4c
456#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d

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557 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
558 if (field & 0x80)
559 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
560 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
561 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
562 dev_cap->fs_max_num_qp_per_entry = field;
563 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
564 dev_cap->stat_rate_support = stat_rate;
565 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
566 if (field & 0x80)
567 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
561 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
562 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
563 dev_cap->flags = flags | (u64)ext_flags << 32;
564 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
565 dev_cap->reserved_uars = field >> 4;
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
567 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
568 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);

--- 1088 unchanged lines hidden --- 		568 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
569 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
570 dev_cap->flags = flags | (u64)ext_flags << 32;
571 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
572 dev_cap->reserved_uars = field >> 4;
573 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
574 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
575 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);

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