fw.c (e4da3fbfbd1de56d2367653e3823e6445e49f8a9) fw.c (f9baff509f8a05a79626defdbdf4f4aa4efd373b)
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file

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134 inbox = mailbox->buf;
135
136 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
137
138 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
139 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
140
141 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file

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134 inbox = mailbox->buf;
135
136 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
137
138 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
139 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
140
141 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
142 MLX4_CMD_TIME_CLASS_A);
142 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
143
144 mlx4_free_cmd_mailbox(dev, mailbox);
145 return err;
146}
147
148int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
149{
150 struct mlx4_cmd_mailbox *mailbox;

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224#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
225
226 mailbox = mlx4_alloc_cmd_mailbox(dev);
227 if (IS_ERR(mailbox))
228 return PTR_ERR(mailbox);
229 outbox = mailbox->buf;
230
231 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
143
144 mlx4_free_cmd_mailbox(dev, mailbox);
145 return err;
146}
147
148int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
149{
150 struct mlx4_cmd_mailbox *mailbox;

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224#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
225
226 mailbox = mlx4_alloc_cmd_mailbox(dev);
227 if (IS_ERR(mailbox))
228 return PTR_ERR(mailbox);
229 outbox = mailbox->buf;
230
231 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
232 MLX4_CMD_TIME_CLASS_A);
232 MLX4_CMD_TIME_CLASS_A, !mlx4_is_slave(dev));
233 if (err)
234 goto out;
235
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
237 dev_cap->reserved_qps = 1 << (field & 0xf);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
239 dev_cap->max_qps = 1 << (field & 0x1f);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);

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391#define QUERY_PORT_MAX_VL_OFFSET 0x0b
392#define QUERY_PORT_MAC_OFFSET 0x10
393#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
394#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
395#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
396
397 for (i = 1; i <= dev_cap->num_ports; ++i) {
398 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
233 if (err)
234 goto out;
235
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
237 dev_cap->reserved_qps = 1 << (field & 0xf);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
239 dev_cap->max_qps = 1 << (field & 0x1f);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);

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391#define QUERY_PORT_MAX_VL_OFFSET 0x0b
392#define QUERY_PORT_MAC_OFFSET 0x10
393#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
394#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
395#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
396
397 for (i = 1; i <= dev_cap->num_ports; ++i) {
398 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
399 MLX4_CMD_TIME_CLASS_B);
399 MLX4_CMD_TIME_CLASS_B,
400 !mlx4_is_slave(dev));
400 if (err)
401 goto out;
402
403 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
404 dev_cap->supported_port_types[i] = field & 3;
405 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
406 dev_cap->ib_mtu[i] = field & 0xf;
407 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);

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514 pages[nent * 2 + 1] =
515 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
516 (lg - MLX4_ICM_PAGE_SHIFT));
517 ts += 1 << (lg - 10);
518 ++tc;
519
520 if (++nent == MLX4_MAILBOX_SIZE / 16) {
521 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
401 if (err)
402 goto out;
403
404 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
405 dev_cap->supported_port_types[i] = field & 3;
406 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
407 dev_cap->ib_mtu[i] = field & 0xf;
408 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);

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515 pages[nent * 2 + 1] =
516 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
517 (lg - MLX4_ICM_PAGE_SHIFT));
518 ts += 1 << (lg - 10);
519 ++tc;
520
521 if (++nent == MLX4_MAILBOX_SIZE / 16) {
522 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
522 MLX4_CMD_TIME_CLASS_B);
523 MLX4_CMD_TIME_CLASS_B,
524 MLX4_CMD_NATIVE);
523 if (err)
524 goto out;
525 nent = 0;
526 }
527 }
528 }
529
530 if (nent)
525 if (err)
526 goto out;
527 nent = 0;
528 }
529 }
530 }
531
532 if (nent)
531 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
533 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
534 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
532 if (err)
533 goto out;
534
535 switch (op) {
536 case MLX4_CMD_MAP_FA:
537 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
538 break;
539 case MLX4_CMD_MAP_ICM_AUX:

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552
553int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
554{
555 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
556}
557
558int mlx4_UNMAP_FA(struct mlx4_dev *dev)
559{
535 if (err)
536 goto out;
537
538 switch (op) {
539 case MLX4_CMD_MAP_FA:
540 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
541 break;
542 case MLX4_CMD_MAP_ICM_AUX:

--- 12 unchanged lines hidden (view full) ---

555
556int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
557{
558 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
559}
560
561int mlx4_UNMAP_FA(struct mlx4_dev *dev)
562{
560 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
563 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
564 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
561}
562
563
564int mlx4_RUN_FW(struct mlx4_dev *dev)
565{
565}
566
567
568int mlx4_RUN_FW(struct mlx4_dev *dev)
569{
566 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
570 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
571 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
567}
568
569int mlx4_QUERY_FW(struct mlx4_dev *dev)
570{
571 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
572 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
573 struct mlx4_cmd_mailbox *mailbox;
574 u32 *outbox;

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590#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
591
592 mailbox = mlx4_alloc_cmd_mailbox(dev);
593 if (IS_ERR(mailbox))
594 return PTR_ERR(mailbox);
595 outbox = mailbox->buf;
596
597 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
572}
573
574int mlx4_QUERY_FW(struct mlx4_dev *dev)
575{
576 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
577 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
578 struct mlx4_cmd_mailbox *mailbox;
579 u32 *outbox;

--- 15 unchanged lines hidden (view full) ---

595#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
596
597 mailbox = mlx4_alloc_cmd_mailbox(dev);
598 if (IS_ERR(mailbox))
599 return PTR_ERR(mailbox);
600 outbox = mailbox->buf;
601
602 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
598 MLX4_CMD_TIME_CLASS_A);
603 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
599 if (err)
600 goto out;
601
602 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
603 /*
604 * FW subminor version is at more significant bits than minor
605 * version, so swap here.
606 */

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706#define QUERY_ADAPTER_VSD_OFFSET 0x20
707
708 mailbox = mlx4_alloc_cmd_mailbox(dev);
709 if (IS_ERR(mailbox))
710 return PTR_ERR(mailbox);
711 outbox = mailbox->buf;
712
713 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
604 if (err)
605 goto out;
606
607 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
608 /*
609 * FW subminor version is at more significant bits than minor
610 * version, so swap here.
611 */

--- 99 unchanged lines hidden (view full) ---

711#define QUERY_ADAPTER_VSD_OFFSET 0x20
712
713 mailbox = mlx4_alloc_cmd_mailbox(dev);
714 if (IS_ERR(mailbox))
715 return PTR_ERR(mailbox);
716 outbox = mailbox->buf;
717
718 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
714 MLX4_CMD_TIME_CLASS_A);
719 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
715 if (err)
716 goto out;
717
718 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
719
720 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
721 adapter->board_id);
722

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829 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
830 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
831
832 /* UAR attributes */
833
834 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
835 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
836
720 if (err)
721 goto out;
722
723 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
724
725 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
726 adapter->board_id);
727

--- 106 unchanged lines hidden (view full) ---

834 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
835 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
836
837 /* UAR attributes */
838
839 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
840 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
841
837 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
842 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
843 MLX4_CMD_NATIVE);
838
839 if (err)
840 mlx4_err(dev, "INIT_HCA returns %d\n", err);
841
842 mlx4_free_cmd_mailbox(dev, mailbox);
843 return err;
844}
845

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881 field = 128 << dev->caps.ib_mtu_cap[port];
882 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
883 field = dev->caps.gid_table_len[port];
884 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
885 field = dev->caps.pkey_table_len[port];
886 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
887
888 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
844
845 if (err)
846 mlx4_err(dev, "INIT_HCA returns %d\n", err);
847
848 mlx4_free_cmd_mailbox(dev, mailbox);
849 return err;
850}
851

--- 35 unchanged lines hidden (view full) ---

887 field = 128 << dev->caps.ib_mtu_cap[port];
888 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
889 field = dev->caps.gid_table_len[port];
890 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
891 field = dev->caps.pkey_table_len[port];
892 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
893
894 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
889 MLX4_CMD_TIME_CLASS_A);
895 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
890
891 mlx4_free_cmd_mailbox(dev, mailbox);
892 } else
893 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
896
897 mlx4_free_cmd_mailbox(dev, mailbox);
898 } else
899 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
894 MLX4_CMD_TIME_CLASS_A);
900 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
895
896 return err;
897}
898EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
899
900int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
901{
901
902 return err;
903}
904EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
905
906int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
907{
902 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
908 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
909 MLX4_CMD_WRAPPED);
903}
904EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
905
906int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
907{
910}
911EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
912
913int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
914{
908 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
915 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
916 MLX4_CMD_NATIVE);
909}
910
911int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
912{
913 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
914 MLX4_CMD_SET_ICM_SIZE,
917}
918
919int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
920{
921 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
922 MLX4_CMD_SET_ICM_SIZE,
915 MLX4_CMD_TIME_CLASS_A);
923 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
916 if (ret)
917 return ret;
918
919 /*
920 * Round up number of system pages needed in case
921 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
922 */
923 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
924 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
925
926 return 0;
927}
928
929int mlx4_NOP(struct mlx4_dev *dev)
930{
931 /* Input modifier of 0x1f means "finish as soon as possible." */
924 if (ret)
925 return ret;
926
927 /*
928 * Round up number of system pages needed in case
929 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
930 */
931 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
932 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
933
934 return 0;
935}
936
937int mlx4_NOP(struct mlx4_dev *dev)
938{
939 /* Input modifier of 0x1f means "finish as soon as possible." */
932 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
940 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
933}
934
935#define MLX4_WOL_SETUP_MODE (5 << 28)
936int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
937{
938 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
939
940 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
941}
942
943#define MLX4_WOL_SETUP_MODE (5 << 28)
944int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
945{
946 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
947
948 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
941 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
949 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
950 MLX4_CMD_NATIVE);
942}
943EXPORT_SYMBOL_GPL(mlx4_wol_read);
944
945int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
946{
947 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
948
949 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
951}
952EXPORT_SYMBOL_GPL(mlx4_wol_read);
953
954int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
955{
956 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
957
958 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
950 MLX4_CMD_TIME_CLASS_A);
959 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
951}
952EXPORT_SYMBOL_GPL(mlx4_wol_write);
960}
961EXPORT_SYMBOL_GPL(mlx4_wol_write);