igc.h (08d99b2c23dfa84ca5b5e5c194062a0550888b71) igc.h (ec50a9d437f05dd76444a65fdd3cfbfad90ee9d6)
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_H_
5#define _IGC_H_
6
7#include <linux/kobject.h>
8#include <linux/pci.h>

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65#define IGC_FLAG_PTP BIT(8)
66#define IGC_FLAG_WOL_SUPPORTED BIT(8)
67#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
68#define IGC_FLAG_MEDIA_RESET BIT(10)
69#define IGC_FLAG_MAS_ENABLE BIT(12)
70#define IGC_FLAG_HAS_MSIX BIT(13)
71#define IGC_FLAG_VLAN_PROMISC BIT(15)
72#define IGC_FLAG_RX_LEGACY BIT(16)
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018 Intel Corporation */
3
4#ifndef _IGC_H_
5#define _IGC_H_
6
7#include <linux/kobject.h>
8#include <linux/pci.h>

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65#define IGC_FLAG_PTP BIT(8)
66#define IGC_FLAG_WOL_SUPPORTED BIT(8)
67#define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
68#define IGC_FLAG_MEDIA_RESET BIT(10)
69#define IGC_FLAG_MAS_ENABLE BIT(12)
70#define IGC_FLAG_HAS_MSIX BIT(13)
71#define IGC_FLAG_VLAN_PROMISC BIT(15)
72#define IGC_FLAG_RX_LEGACY BIT(16)
73#define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
73
74#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
75#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
76
77#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
78#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
79#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
80

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282 dma_addr_t dma; /* phys address of the ring */
283 unsigned int size; /* length of desc. ring in bytes */
284
285 u16 count; /* number of desc. in the ring */
286 u8 queue_index; /* logical index of the ring*/
287 u8 reg_idx; /* physical index of the ring */
288 bool launchtime_enable; /* true if LaunchTime is enabled */
289
74
75#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
76#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
77
78#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
79#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
80#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
81

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283 dma_addr_t dma; /* phys address of the ring */
284 unsigned int size; /* length of desc. ring in bytes */
285
286 u16 count; /* number of desc. in the ring */
287 u8 queue_index; /* logical index of the ring*/
288 u8 reg_idx; /* physical index of the ring */
289 bool launchtime_enable; /* true if LaunchTime is enabled */
290
291 u32 start_time;
292 u32 end_time;
293
290 /* everything past this point are written often */
291 u16 next_to_clean;
292 u16 next_to_use;
293 u16 next_to_alloc;
294
295 union {
296 /* TX */
297 struct {

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416 bool fc_autoneg;
417
418 u8 tx_timeout_factor;
419
420 int msg_enable;
421 u32 max_frame_size;
422 u32 min_frame_size;
423
294 /* everything past this point are written often */
295 u16 next_to_clean;
296 u16 next_to_use;
297 u16 next_to_alloc;
298
299 union {
300 /* TX */
301 struct {

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420 bool fc_autoneg;
421
422 u8 tx_timeout_factor;
423
424 int msg_enable;
425 u32 max_frame_size;
426 u32 min_frame_size;
427
428 ktime_t base_time;
429 ktime_t cycle_time;
430
424 /* OS defined structs */
425 struct pci_dev *pdev;
426 /* lock for statistics */
427 spinlock_t stats64_lock;
428 struct rtnl_link_stats64 stats64;
429
430 /* structs defined in igc_hw.h */
431 struct igc_hw hw;

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432 struct pci_dev *pdev;
433 /* lock for statistics */
434 spinlock_t stats64_lock;
435 struct rtnl_link_stats64 stats64;
436
437 /* structs defined in igc_hw.h */
438 struct igc_hw hw;

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