igb.h (f69aa3909eeb8444f9b980f6315696c3b0bb57d5) igb.h (b980ac18c95f3251038da7a3826370aff05a7434)
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.

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39#include <linux/ptp_clock_kernel.h>
40#include <linux/bitops.h>
41#include <linux/if_vlan.h>
42#include <linux/i2c.h>
43#include <linux/i2c-algo-bit.h>
44
45struct igb_adapter;
46
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.

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39#include <linux/ptp_clock_kernel.h>
40#include <linux/bitops.h>
41#include <linux/if_vlan.h>
42#include <linux/i2c.h>
43#include <linux/i2c-algo-bit.h>
44
45struct igb_adapter;
46
47#define E1000_PCS_CFG_IGN_SD 1
47#define E1000_PCS_CFG_IGN_SD 1
48
49/* Interrupt defines */
48
49/* Interrupt defines */
50#define IGB_START_ITR 648 /* ~6000 ints/sec */
51#define IGB_4K_ITR 980
52#define IGB_20K_ITR 196
53#define IGB_70K_ITR 56
50#define IGB_START_ITR 648 /* ~6000 ints/sec */
51#define IGB_4K_ITR 980
52#define IGB_20K_ITR 196
53#define IGB_70K_ITR 56
54
55/* TX/RX descriptor defines */
54
55/* TX/RX descriptor defines */
56#define IGB_DEFAULT_TXD 256
57#define IGB_DEFAULT_TX_WORK 128
58#define IGB_MIN_TXD 80
59#define IGB_MAX_TXD 4096
56#define IGB_DEFAULT_TXD 256
57#define IGB_DEFAULT_TX_WORK 128
58#define IGB_MIN_TXD 80
59#define IGB_MAX_TXD 4096
60
60
61#define IGB_DEFAULT_RXD 256
62#define IGB_MIN_RXD 80
63#define IGB_MAX_RXD 4096
61#define IGB_DEFAULT_RXD 256
62#define IGB_MIN_RXD 80
63#define IGB_MAX_RXD 4096
64
64
65#define IGB_DEFAULT_ITR 3 /* dynamic */
66#define IGB_MAX_ITR_USECS 10000
67#define IGB_MIN_ITR_USECS 10
68#define NON_Q_VECTORS 1
69#define MAX_Q_VECTORS 8
65#define IGB_DEFAULT_ITR 3 /* dynamic */
66#define IGB_MAX_ITR_USECS 10000
67#define IGB_MIN_ITR_USECS 10
68#define NON_Q_VECTORS 1
69#define MAX_Q_VECTORS 8
70
71/* Transmit and receive queues */
70
71/* Transmit and receive queues */
72#define IGB_MAX_RX_QUEUES 8
73#define IGB_MAX_RX_QUEUES_82575 4
74#define IGB_MAX_RX_QUEUES_I211 2
75#define IGB_MAX_TX_QUEUES 8
76#define IGB_MAX_VF_MC_ENTRIES 30
77#define IGB_MAX_VF_FUNCTIONS 8
78#define IGB_MAX_VFTA_ENTRIES 128
79#define IGB_82576_VF_DEV_ID 0x10CA
80#define IGB_I350_VF_DEV_ID 0x1520
72#define IGB_MAX_RX_QUEUES 8
73#define IGB_MAX_RX_QUEUES_82575 4
74#define IGB_MAX_RX_QUEUES_I211 2
75#define IGB_MAX_TX_QUEUES 8
76#define IGB_MAX_VF_MC_ENTRIES 30
77#define IGB_MAX_VF_FUNCTIONS 8
78#define IGB_MAX_VFTA_ENTRIES 128
79#define IGB_82576_VF_DEV_ID 0x10CA
80#define IGB_I350_VF_DEV_ID 0x1520
81
82/* NVM version defines */
81
82/* NVM version defines */
83#define IGB_MAJOR_MASK 0xF000
84#define IGB_MINOR_MASK 0x0FF0
85#define IGB_BUILD_MASK 0x000F
86#define IGB_COMB_VER_MASK 0x00FF
87#define IGB_MAJOR_SHIFT 12
88#define IGB_MINOR_SHIFT 4
89#define IGB_COMB_VER_SHFT 8
90#define IGB_NVM_VER_INVALID 0xFFFF
91#define IGB_ETRACK_SHIFT 16
92#define NVM_ETRACK_WORD 0x0042
93#define NVM_COMB_VER_OFF 0x0083
94#define NVM_COMB_VER_PTR 0x003d
83#define IGB_MAJOR_MASK 0xF000
84#define IGB_MINOR_MASK 0x0FF0
85#define IGB_BUILD_MASK 0x000F
86#define IGB_COMB_VER_MASK 0x00FF
87#define IGB_MAJOR_SHIFT 12
88#define IGB_MINOR_SHIFT 4
89#define IGB_COMB_VER_SHFT 8
90#define IGB_NVM_VER_INVALID 0xFFFF
91#define IGB_ETRACK_SHIFT 16
92#define NVM_ETRACK_WORD 0x0042
93#define NVM_COMB_VER_OFF 0x0083
94#define NVM_COMB_VER_PTR 0x003d
95
96struct vf_data_storage {
97 unsigned char vf_mac_addresses[ETH_ALEN];
98 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
99 u16 num_vf_mc_hashes;
100 u16 vlans_enabled;
101 u32 flags;
102 unsigned long last_nack;

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116 * Setting this to 0 disables RX descriptor prefetch.
117 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
118 * available in host memory.
119 * If PTHRESH is 0, this should also be 0.
120 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
121 * descriptors until either it has this many to write back, or the
122 * ITR timer expires.
123 */
95
96struct vf_data_storage {
97 unsigned char vf_mac_addresses[ETH_ALEN];
98 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
99 u16 num_vf_mc_hashes;
100 u16 vlans_enabled;
101 u32 flags;
102 unsigned long last_nack;

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116 * Setting this to 0 disables RX descriptor prefetch.
117 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
118 * available in host memory.
119 * If PTHRESH is 0, this should also be 0.
120 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
121 * descriptors until either it has this many to write back, or the
122 * ITR timer expires.
123 */
124#define IGB_RX_PTHRESH 8
125#define IGB_RX_HTHRESH 8
126#define IGB_TX_PTHRESH 8
127#define IGB_TX_HTHRESH 1
128#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
129 adapter->msix_entries) ? 1 : 4)
130#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
131 adapter->msix_entries) ? 1 : 16)
124#define IGB_RX_PTHRESH 8
125#define IGB_RX_HTHRESH 8
126#define IGB_TX_PTHRESH 8
127#define IGB_TX_HTHRESH 1
128#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
129 adapter->msix_entries) ? 1 : 4)
130#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
131 adapter->msix_entries) ? 1 : 16)
132
133/* this is the size past which hardware will drop packets when setting LPE=0 */
134#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
135
136/* Supported Rx Buffer Sizes */
137#define IGB_RXBUFFER_256 256
138#define IGB_RXBUFFER_2048 2048
139#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
140#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
141
142/* How many Rx Buffers do we bundle into one write to the hardware ? */
132
133/* this is the size past which hardware will drop packets when setting LPE=0 */
134#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
135
136/* Supported Rx Buffer Sizes */
137#define IGB_RXBUFFER_256 256
138#define IGB_RXBUFFER_2048 2048
139#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
140#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
141
142/* How many Rx Buffers do we bundle into one write to the hardware ? */
143#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
143#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
144
144
145#define AUTO_ALL_MODES 0
146#define IGB_EEPROM_APME 0x0400
145#define AUTO_ALL_MODES 0
146#define IGB_EEPROM_APME 0x0400
147
148#ifndef IGB_MASTER_SLAVE
149/* Switch to override PHY master/slave setting */
150#define IGB_MASTER_SLAVE e1000_ms_hw_default
151#endif
152
147
148#ifndef IGB_MASTER_SLAVE
149/* Switch to override PHY master/slave setting */
150#define IGB_MASTER_SLAVE e1000_ms_hw_default
151#endif
152
153#define IGB_MNG_VLAN_NONE -1
153#define IGB_MNG_VLAN_NONE -1
154
155enum igb_tx_flags {
156 /* cmd_type flags */
157 IGB_TX_FLAGS_VLAN = 0x01,
158 IGB_TX_FLAGS_TSO = 0x02,
159 IGB_TX_FLAGS_TSTAMP = 0x04,
160
161 /* olinfo flags */
162 IGB_TX_FLAGS_IPV4 = 0x10,
163 IGB_TX_FLAGS_CSUM = 0x20,
164};
165
166/* VLAN info */
154
155enum igb_tx_flags {
156 /* cmd_type flags */
157 IGB_TX_FLAGS_VLAN = 0x01,
158 IGB_TX_FLAGS_TSO = 0x02,
159 IGB_TX_FLAGS_TSTAMP = 0x04,
160
161 /* olinfo flags */
162 IGB_TX_FLAGS_IPV4 = 0x10,
163 IGB_TX_FLAGS_CSUM = 0x20,
164};
165
166/* VLAN info */
167#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
167#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
168#define IGB_TX_FLAGS_VLAN_SHIFT 16
169
168#define IGB_TX_FLAGS_VLAN_SHIFT 16
169
170/*
171 * The largest size we can write to the descriptor is 65535. In order to
170/* The largest size we can write to the descriptor is 65535. In order to
172 * maintain a power of two alignment we have to limit ourselves to 32K.
173 */
174#define IGB_MAX_TXD_PWR 15
175#define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)
176
177/* Tx Descriptors needed, worst case */
178#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
179#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
180
181/* EEPROM byte offsets */
182#define IGB_SFF_8472_SWAP 0x5C
183#define IGB_SFF_8472_COMP 0x5E
184
185/* Bitmasks */
186#define IGB_SFF_ADDRESSING_MODE 0x4
187#define IGB_SFF_8472_UNSUP 0x00
188
189/* wrapper around a pointer to a socket buffer,
171 * maintain a power of two alignment we have to limit ourselves to 32K.
172 */
173#define IGB_MAX_TXD_PWR 15
174#define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)
175
176/* Tx Descriptors needed, worst case */
177#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
178#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
179
180/* EEPROM byte offsets */
181#define IGB_SFF_8472_SWAP 0x5C
182#define IGB_SFF_8472_COMP 0x5E
183
184/* Bitmasks */
185#define IGB_SFF_ADDRESSING_MODE 0x4
186#define IGB_SFF_8472_UNSUP 0x00
187
188/* wrapper around a pointer to a socket buffer,
190 * so a DMA handle can be stored along with the buffer */
189 * so a DMA handle can be stored along with the buffer
190 */
191struct igb_tx_buffer {
192 union e1000_adv_tx_desc *next_to_watch;
193 unsigned long time_stamp;
194 struct sk_buff *skb;
195 unsigned int bytecount;
196 u16 gso_segs;
197 __be16 protocol;
198 DEFINE_DMA_UNMAP_ADDR(dma);

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301 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
302#define set_ring_build_skb_enabled(ring) \
303 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
304#define clear_ring_build_skb_enabled(ring) \
305 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
306
307#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
308
191struct igb_tx_buffer {
192 union e1000_adv_tx_desc *next_to_watch;
193 unsigned long time_stamp;
194 struct sk_buff *skb;
195 unsigned int bytecount;
196 u16 gso_segs;
197 __be16 protocol;
198 DEFINE_DMA_UNMAP_ADDR(dma);

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301 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
302#define set_ring_build_skb_enabled(ring) \
303 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
304#define clear_ring_build_skb_enabled(ring) \
305 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
306
307#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
308
309#define IGB_RX_DESC(R, i) \
309#define IGB_RX_DESC(R, i) \
310 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
310 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
311#define IGB_TX_DESC(R, i) \
311#define IGB_TX_DESC(R, i) \
312 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
312 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
313#define IGB_TX_CTXTDESC(R, i) \
313#define IGB_TX_CTXTDESC(R, i) \
314 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
315
316/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
317static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
318 const u32 stat_err_bits)
319{
320 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
321}

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464#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
465#define IGB_FLAG_DMAC (1 << 4)
466#define IGB_FLAG_PTP (1 << 5)
467#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
468#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
469#define IGB_FLAG_WOL_SUPPORTED (1 << 8)
470
471/* DMA Coalescing defines */
314 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
315
316/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
317static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
318 const u32 stat_err_bits)
319{
320 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
321}

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464#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
465#define IGB_FLAG_DMAC (1 << 4)
466#define IGB_FLAG_PTP (1 << 5)
467#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
468#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
469#define IGB_FLAG_WOL_SUPPORTED (1 << 8)
470
471/* DMA Coalescing defines */
472#define IGB_MIN_TXPBSIZE 20408
473#define IGB_TX_BUF_4096 4096
474#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
472#define IGB_MIN_TXPBSIZE 20408
473#define IGB_TX_BUF_4096 4096
474#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
475
475
476#define IGB_82576_TSYNC_SHIFT 19
477#define IGB_TS_HDR_LEN 16
476#define IGB_82576_TSYNC_SHIFT 19
477#define IGB_TS_HDR_LEN 16
478enum e1000_state_t {
479 __IGB_TESTING,
480 __IGB_RESETTING,
481 __IGB_DOWN
482};
483
484enum igb_boards {
485 board_82575,

--- 91 unchanged lines hidden --- 		478enum e1000_state_t {
479 __IGB_TESTING,
480 __IGB_RESETTING,
481 __IGB_DOWN
482};
483
484enum igb_boards {
485 board_82575,

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