| macb.h (65d2918e716afb89359cfa59734d76c1ff8700cb) | macb.h (a50dad355a5314da64586da36804b86fbebb7c2a) |
|---|---|
| 1/* 2 * Atmel MACB Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 215 unchanged lines hidden (view full) --- 224/* Constants for data bus width. */ 225#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 226#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 227#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 228 229/* Bitfields in DMACFG. */ 230#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 231#define GEM_FBLDO_SIZE 5 | 1/* 2 * Atmel MACB Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 215 unchanged lines hidden (view full) --- 224/* Constants for data bus width. */ 225#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 226#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 227#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 228 229/* Bitfields in DMACFG. */ 230#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 231#define GEM_FBLDO_SIZE 5 |
| 232#define GEM_ENDIA_OFFSET 7 /* endian swap mode for packet data access */ | 232#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 233#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ |
| 233#define GEM_ENDIA_SIZE 1 234#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 235#define GEM_RXBMS_SIZE 2 236#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 237#define GEM_TXPBMS_SIZE 1 238#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 239#define GEM_TXCOEN_SIZE 1 240#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ --- 177 unchanged lines hidden (view full) --- 418 & ((1 << GEM_##name##_SIZE) - 1)) 419#define GEM_BFINS(name, value, old) \ 420 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 421 << GEM_##name##_OFFSET)) \ 422 | GEM_BF(name, value)) 423 424/* Register access macros */ 425#define macb_readl(port,reg) \ | 234#define GEM_ENDIA_SIZE 1 235#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 236#define GEM_RXBMS_SIZE 2 237#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 238#define GEM_TXPBMS_SIZE 1 239#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 240#define GEM_TXCOEN_SIZE 1 241#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ --- 177 unchanged lines hidden (view full) --- 419 & ((1 << GEM_##name##_SIZE) - 1)) 420#define GEM_BFINS(name, value, old) \ 421 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 422 << GEM_##name##_OFFSET)) \ 423 | GEM_BF(name, value)) 424 425/* Register access macros */ 426#define macb_readl(port,reg) \ |
| 426 __raw_readl((port)->regs + MACB_##reg) | 427 readl_relaxed((port)->regs + MACB_##reg) |
| 427#define macb_writel(port,reg,value) \ | 428#define macb_writel(port,reg,value) \ |
| 428 __raw_writel((value), (port)->regs + MACB_##reg) | 429 writel_relaxed((value), (port)->regs + MACB_##reg) |
| 429#define gem_readl(port, reg) \ | 430#define gem_readl(port, reg) \ |
| 430 __raw_readl((port)->regs + GEM_##reg) | 431 readl_relaxed((port)->regs + GEM_##reg) |
| 431#define gem_writel(port, reg, value) \ | 432#define gem_writel(port, reg, value) \ |
| 432 __raw_writel((value), (port)->regs + GEM_##reg) | 433 writel_relaxed((value), (port)->regs + GEM_##reg) |
| 433#define queue_readl(queue, reg) \ | 434#define queue_readl(queue, reg) \ |
| 434 __raw_readl((queue)->bp->regs + (queue)->reg) | 435 readl_relaxed((queue)->bp->regs + (queue)->reg) |
| 435#define queue_writel(queue, reg, value) \ | 436#define queue_writel(queue, reg, value) \ |
| 436 __raw_writel((value), (queue)->bp->regs + (queue)->reg) | 437 writel_relaxed((value), (queue)->bp->regs + (queue)->reg) |
| 437 438/* Conditional GEM/MACB macros. These perform the operation to the correct 439 * register dependent on whether the device is a GEM or a MACB. For registers 440 * and bitfields that are common across both devices, use macb_{read,write}l 441 * to avoid the cost of the conditional. 442 */ 443#define macb_or_gem_writel(__bp, __reg, __value) \ 444 ({ \ --- 393 unchanged lines hidden --- | 438 439/* Conditional GEM/MACB macros. These perform the operation to the correct 440 * register dependent on whether the device is a GEM or a MACB. For registers 441 * and bitfields that are common across both devices, use macb_{read,write}l 442 * to avoid the cost of the conditional. 443 */ 444#define macb_or_gem_writel(__bp, __reg, __value) \ 445 ({ \ --- 393 unchanged lines hidden --- |