macb.h (300e812db26f4aa022e346f5fb9af1af134d98d8) macb.h (f75ba50bdc2bcfab591bdf903312557033d0ac68)
1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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54#define MACB_SA3B 0x00a8
55#define MACB_SA3T 0x00ac
56#define MACB_SA4B 0x00b0
57#define MACB_SA4T 0x00b4
58#define MACB_TID 0x00b8
59#define MACB_TPQ 0x00bc
60#define MACB_USRIO 0x00c0
61#define MACB_WOL 0x00c4
1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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54#define MACB_SA3B 0x00a8
55#define MACB_SA3T 0x00ac
56#define MACB_SA4B 0x00b0
57#define MACB_SA4T 0x00b4
58#define MACB_TID 0x00b8
59#define MACB_TPQ 0x00bc
60#define MACB_USRIO 0x00c0
61#define MACB_WOL 0x00c4
62#define MACB_MID 0x00fc
62
63
64/* GEM register offsets. */
65#define GEM_NCFGR 0x0004
66#define GEM_USRIO 0x000c
67#define GEM_HRB 0x0080
68#define GEM_HRT 0x0084
69#define GEM_SA1B 0x0088
70#define GEM_SA1T 0x008C
71
63/* Bitfields in NCR */
64#define MACB_LB_OFFSET 0
65#define MACB_LB_SIZE 1
66#define MACB_LLB_OFFSET 1
67#define MACB_LLB_SIZE 1
68#define MACB_RE_OFFSET 2
69#define MACB_RE_SIZE 1
70#define MACB_TE_OFFSET 3

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223#define MACB_MAG_SIZE 1
224#define MACB_ARP_OFFSET 17
225#define MACB_ARP_SIZE 1
226#define MACB_SA1_OFFSET 18
227#define MACB_SA1_SIZE 1
228#define MACB_WOL_MTI_OFFSET 19
229#define MACB_WOL_MTI_SIZE 1
230
72/* Bitfields in NCR */
73#define MACB_LB_OFFSET 0
74#define MACB_LB_SIZE 1
75#define MACB_LLB_OFFSET 1
76#define MACB_LLB_SIZE 1
77#define MACB_RE_OFFSET 2
78#define MACB_RE_SIZE 1
79#define MACB_TE_OFFSET 3

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232#define MACB_MAG_SIZE 1
233#define MACB_ARP_OFFSET 17
234#define MACB_ARP_SIZE 1
235#define MACB_SA1_OFFSET 18
236#define MACB_SA1_SIZE 1
237#define MACB_WOL_MTI_OFFSET 19
238#define MACB_WOL_MTI_SIZE 1
239
240/* Bitfields in MID */
241#define MACB_IDNUM_OFFSET 16
242#define MACB_IDNUM_SIZE 16
243#define MACB_REV_OFFSET 0
244#define MACB_REV_SIZE 16
245
231/* Constants for CLK */
232#define MACB_CLK_DIV8 0
233#define MACB_CLK_DIV16 1
234#define MACB_CLK_DIV32 2
235#define MACB_CLK_DIV64 3
236
237/* Constants for MAN register */
238#define MACB_MAN_SOF 1

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249#define MACB_BFEXT(name,value)\
250 (((value) >> MACB_##name##_OFFSET) \
251 & ((1 << MACB_##name##_SIZE) - 1))
252#define MACB_BFINS(name,value,old) \
253 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
254 << MACB_##name##_OFFSET)) \
255 | MACB_BF(name,value))
256
246/* Constants for CLK */
247#define MACB_CLK_DIV8 0
248#define MACB_CLK_DIV16 1
249#define MACB_CLK_DIV32 2
250#define MACB_CLK_DIV64 3
251
252/* Constants for MAN register */
253#define MACB_MAN_SOF 1

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264#define MACB_BFEXT(name,value)\
265 (((value) >> MACB_##name##_OFFSET) \
266 & ((1 << MACB_##name##_SIZE) - 1))
267#define MACB_BFINS(name,value,old) \
268 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
269 << MACB_##name##_OFFSET)) \
270 | MACB_BF(name,value))
271
272#define GEM_BIT(name) \
273 (1 << GEM_##name##_OFFSET)
274#define GEM_BF(name, value) \
275 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
276 << GEM_##name##_OFFSET)
277#define GEM_BFEXT(name, value)\
278 (((value) >> GEM_##name##_OFFSET) \
279 & ((1 << GEM_##name##_SIZE) - 1))
280#define GEM_BFINS(name, value, old) \
281 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
282 << GEM_##name##_OFFSET)) \
283 | GEM_BF(name, value))
284
257/* Register access macros */
258#define macb_readl(port,reg) \
259 __raw_readl((port)->regs + MACB_##reg)
260#define macb_writel(port,reg,value) \
261 __raw_writel((value), (port)->regs + MACB_##reg)
285/* Register access macros */
286#define macb_readl(port,reg) \
287 __raw_readl((port)->regs + MACB_##reg)
288#define macb_writel(port,reg,value) \
289 __raw_writel((value), (port)->regs + MACB_##reg)
290#define gem_readl(port, reg) \
291 __raw_readl((port)->regs + GEM_##reg)
292#define gem_writel(port, reg, value) \
293 __raw_writel((value), (port)->regs + GEM_##reg)
262
294
295/*
296 * Conditional GEM/MACB macros. These perform the operation to the correct
297 * register dependent on whether the device is a GEM or a MACB. For registers
298 * and bitfields that are common across both devices, use macb_{read,write}l
299 * to avoid the cost of the conditional.
300 */
301#define macb_or_gem_writel(__bp, __reg, __value) \
302 ({ \
303 if (macb_is_gem((__bp))) \
304 gem_writel((__bp), __reg, __value); \
305 else \
306 macb_writel((__bp), __reg, __value); \
307 })
308
309#define macb_or_gem_readl(__bp, __reg) \
310 ({ \
311 u32 __v; \
312 if (macb_is_gem((__bp))) \
313 __v = gem_readl((__bp), __reg); \
314 else \
315 __v = macb_readl((__bp), __reg); \
316 __v; \
317 })
318
263struct dma_desc {
264 u32 addr;
265 u32 ctrl;
266};
267
268/* DMA descriptor bitfields */
269#define MACB_RX_USED_OFFSET 0
270#define MACB_RX_USED_SIZE 1

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386
387 struct mii_bus *mii_bus;
388 struct phy_device *phy_dev;
389 unsigned int link;
390 unsigned int speed;
391 unsigned int duplex;
392};
393
319struct dma_desc {
320 u32 addr;
321 u32 ctrl;
322};
323
324/* DMA descriptor bitfields */
325#define MACB_RX_USED_OFFSET 0
326#define MACB_RX_USED_SIZE 1

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442
443 struct mii_bus *mii_bus;
444 struct phy_device *phy_dev;
445 unsigned int link;
446 unsigned int speed;
447 unsigned int duplex;
448};
449
450static inline bool macb_is_gem(struct macb *bp)
451{
452 return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;
453}
454
394#endif /* _MACB_H */
455#endif /* _MACB_H */