bnx2x.h (cf9ce948f47640797bd19980e1d99c6d17d0bdc3) bnx2x.h (6411280ac94db94a09770807d3871d2661803604)
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
17#include <linux/pci.h>
16#include <linux/netdevice.h>
17#include <linux/dma-mapping.h>
18#include <linux/types.h>
18#include <linux/netdevice.h>
19#include <linux/dma-mapping.h>
20#include <linux/types.h>
21#include <linux/pci_regs.h>
19
20/* compilation time flags */
21
22/* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24/* #define BNX2X_STOP_ON_ERROR */
25
22
23/* compilation time flags */
24
25/* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27/* #define BNX2X_STOP_ON_ERROR */
28
26#define DRV_MODULE_VERSION "1.78.00-0"
27#define DRV_MODULE_RELDATE "2012/09/27"
29#define DRV_MODULE_VERSION "1.78.01-0"
30#define DRV_MODULE_RELDATE "2012/10/30"
28#define BNX2X_BC_VER 0x040200
29
30#if defined(CONFIG_DCB)
31#define BCM_DCBNL
32#endif
33
34
35#include "bnx2x_hsi.h"

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43
44#include "bnx2x_reg.h"
45#include "bnx2x_fw_defs.h"
46#include "bnx2x_mfw_req.h"
47#include "bnx2x_link.h"
48#include "bnx2x_sp.h"
49#include "bnx2x_dcb.h"
50#include "bnx2x_stats.h"
31#define BNX2X_BC_VER 0x040200
32
33#if defined(CONFIG_DCB)
34#define BCM_DCBNL
35#endif
36
37
38#include "bnx2x_hsi.h"

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46
47#include "bnx2x_reg.h"
48#include "bnx2x_fw_defs.h"
49#include "bnx2x_mfw_req.h"
50#include "bnx2x_link.h"
51#include "bnx2x_sp.h"
52#include "bnx2x_dcb.h"
53#include "bnx2x_stats.h"
54#include "bnx2x_vfpf.h"
51
55
56enum bnx2x_int_mode {
57 BNX2X_INT_MODE_MSIX,
58 BNX2X_INT_MODE_INTX,
59 BNX2X_INT_MODE_MSI
60};
61
52/* error/debug prints */
53
54#define DRV_MODULE_NAME "bnx2x"
55
56/* for messages that are currently off */
57#define BNX2X_MSG_OFF 0x0
58#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
59#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */

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329#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
330#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
331
332#define PAGES_PER_SGE_SHIFT 0
333#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
334#define SGE_PAGE_SIZE PAGE_SIZE
335#define SGE_PAGE_SHIFT PAGE_SHIFT
336#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
62/* error/debug prints */
63
64#define DRV_MODULE_NAME "bnx2x"
65
66/* for messages that are currently off */
67#define BNX2X_MSG_OFF 0x0
68#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
69#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */

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339#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
340#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
341
342#define PAGES_PER_SGE_SHIFT 0
343#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
344#define SGE_PAGE_SIZE PAGE_SIZE
345#define SGE_PAGE_SHIFT PAGE_SHIFT
346#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
347#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
348#define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
349 SGE_PAGES), 0xffff)
337
338/* SGE ring related macros */
339#define NUM_RX_SGE_PAGES 2
340#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
341#define NEXT_PAGE_SGE_DESC_CNT 2
342#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
343/* RX_SGE_CNT is promised to be a power of 2 */
344#define RX_SGE_MASK (RX_SGE_CNT - 1)

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784#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
785
786#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
787#define CHIP_NUM_57710 0x164e
788#define CHIP_NUM_57711 0x164f
789#define CHIP_NUM_57711E 0x1650
790#define CHIP_NUM_57712 0x1662
791#define CHIP_NUM_57712_MF 0x1663
350
351/* SGE ring related macros */
352#define NUM_RX_SGE_PAGES 2
353#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
354#define NEXT_PAGE_SGE_DESC_CNT 2
355#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
356/* RX_SGE_CNT is promised to be a power of 2 */
357#define RX_SGE_MASK (RX_SGE_CNT - 1)

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797#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
798
799#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
800#define CHIP_NUM_57710 0x164e
801#define CHIP_NUM_57711 0x164f
802#define CHIP_NUM_57711E 0x1650
803#define CHIP_NUM_57712 0x1662
804#define CHIP_NUM_57712_MF 0x1663
805#define CHIP_NUM_57712_VF 0x166f
792#define CHIP_NUM_57713 0x1651
793#define CHIP_NUM_57713E 0x1652
794#define CHIP_NUM_57800 0x168a
795#define CHIP_NUM_57800_MF 0x16a5
806#define CHIP_NUM_57713 0x1651
807#define CHIP_NUM_57713E 0x1652
808#define CHIP_NUM_57800 0x168a
809#define CHIP_NUM_57800_MF 0x16a5
810#define CHIP_NUM_57800_VF 0x16a9
796#define CHIP_NUM_57810 0x168e
797#define CHIP_NUM_57810_MF 0x16ae
811#define CHIP_NUM_57810 0x168e
812#define CHIP_NUM_57810_MF 0x16ae
813#define CHIP_NUM_57810_VF 0x16af
798#define CHIP_NUM_57811 0x163d
799#define CHIP_NUM_57811_MF 0x163e
814#define CHIP_NUM_57811 0x163d
815#define CHIP_NUM_57811_MF 0x163e
816#define CHIP_NUM_57811_VF 0x163f
800#define CHIP_NUM_57840_OBSOLETE 0x168d
801#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
802#define CHIP_NUM_57840_4_10 0x16a1
803#define CHIP_NUM_57840_2_20 0x16a2
804#define CHIP_NUM_57840_MF 0x16a4
817#define CHIP_NUM_57840_OBSOLETE 0x168d
818#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
819#define CHIP_NUM_57840_4_10 0x16a1
820#define CHIP_NUM_57840_2_20 0x16a2
821#define CHIP_NUM_57840_MF 0x16a4
822#define CHIP_NUM_57840_VF 0x16ad
805#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
806#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
807#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
808#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
823#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
824#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
825#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
826#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
827#define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
809#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
810#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
811#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
828#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
829#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
830#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
831#define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
812#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
813#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
832#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
833#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
834#define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
814#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
815#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
835#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
836#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
837#define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
816#define CHIP_IS_57840(bp) \
817 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
818 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
819 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
820#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
821 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
838#define CHIP_IS_57840(bp) \
839 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
840 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
841 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
842#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
843 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
844#define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
822#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
823 CHIP_IS_57711E(bp))
824#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
825 CHIP_IS_57712_MF(bp))
826#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
827 CHIP_IS_57800_MF(bp) || \
828 CHIP_IS_57810(bp) || \
829 CHIP_IS_57810_MF(bp) || \
845#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
846 CHIP_IS_57711E(bp))
847#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
848 CHIP_IS_57712_MF(bp))
849#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
850 CHIP_IS_57800_MF(bp) || \
851 CHIP_IS_57810(bp) || \
852 CHIP_IS_57810_MF(bp) || \
853 CHIP_IS_57810_VF(bp) || \
830 CHIP_IS_57811(bp) || \
831 CHIP_IS_57811_MF(bp) || \
854 CHIP_IS_57811(bp) || \
855 CHIP_IS_57811_MF(bp) || \
856 CHIP_IS_57811_VF(bp) || \
832 CHIP_IS_57840(bp) || \
857 CHIP_IS_57840(bp) || \
833 CHIP_IS_57840_MF(bp))
858 CHIP_IS_57840_MF(bp) || \
859 CHIP_IS_57840_VF(bp))
834#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
835#define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
836#define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
837
838#define CHIP_REV_SHIFT 12
839#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
840#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
841#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)

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949 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
950
951/* slow path */
952
953/* slow path work-queue */
954extern struct workqueue_struct *bnx2x_wq;
955
956#define BNX2X_MAX_NUM_OF_VFS 64
860#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
861#define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
862#define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
863
864#define CHIP_REV_SHIFT 12
865#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
866#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
867#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)

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975 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
976
977/* slow path */
978
979/* slow path work-queue */
980extern struct workqueue_struct *bnx2x_wq;
981
982#define BNX2X_MAX_NUM_OF_VFS 64
983#define BNX2X_VF_CID_WND 0
984#define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
985#define BNX2X_CLIENTS_PER_VF 1
986#define BNX2X_FIRST_VF_CID 256
987#define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
957#define BNX2X_VF_ID_INVALID 0xFF
958
959/*
960 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
961 * control by the number of fast-path status blocks supported by the
962 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
963 * status block represents an independent interrupts context that can
964 * serve a regular L2 networking queue. However special L2 queues such

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1099 union cdu_context *vcxt;
1100 dma_addr_t cxt_mapping;
1101 size_t size;
1102};
1103
1104/* forward */
1105struct bnx2x_ilt;
1106
988#define BNX2X_VF_ID_INVALID 0xFF
989
990/*
991 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
992 * control by the number of fast-path status blocks supported by the
993 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
994 * status block represents an independent interrupts context that can
995 * serve a regular L2 networking queue. However special L2 queues such

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1130 union cdu_context *vcxt;
1131 dma_addr_t cxt_mapping;
1132 size_t size;
1133};
1134
1135/* forward */
1136struct bnx2x_ilt;
1137
1138struct bnx2x_vfdb;
1107
1108enum bnx2x_recovery_state {
1109 BNX2X_RECOVERY_DONE,
1110 BNX2X_RECOVERY_INIT,
1111 BNX2X_RECOVERY_WAIT,
1112 BNX2X_RECOVERY_FAILED,
1113 BNX2X_RECOVERY_NIC_LOADING
1114};

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1171 struct fcoe_statistics_params fcoe;
1172 struct per_queue_stats queue_stats[1];
1173};
1174
1175/* Public slow path states */
1176enum {
1177 BNX2X_SP_RTNL_SETUP_TC,
1178 BNX2X_SP_RTNL_TX_TIMEOUT,
1139
1140enum bnx2x_recovery_state {
1141 BNX2X_RECOVERY_DONE,
1142 BNX2X_RECOVERY_INIT,
1143 BNX2X_RECOVERY_WAIT,
1144 BNX2X_RECOVERY_FAILED,
1145 BNX2X_RECOVERY_NIC_LOADING
1146};

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1203 struct fcoe_statistics_params fcoe;
1204 struct per_queue_stats queue_stats[1];
1205};
1206
1207/* Public slow path states */
1208enum {
1209 BNX2X_SP_RTNL_SETUP_TC,
1210 BNX2X_SP_RTNL_TX_TIMEOUT,
1179 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1180 BNX2X_SP_RTNL_FAN_FAILURE,
1211 BNX2X_SP_RTNL_FAN_FAILURE,
1212 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1213 BNX2X_SP_RTNL_ENABLE_SRIOV,
1214 BNX2X_SP_RTNL_VFPF_MCAST,
1215 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
1181};
1182
1183
1184struct bnx2x_prev_path_list {
1185 u8 bus;
1186 u8 slot;
1187 u8 path;
1188 struct list_head list;

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1226#define BP_ABS_FUNC(bp) (bp->pf_num)
1227#define BP_VN(bp) ((bp)->pfid >> 1)
1228#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1229#define BP_L_ID(bp) (BP_VN(bp) << 2)
1230#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1231 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1232#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1233
1216};
1217
1218
1219struct bnx2x_prev_path_list {
1220 u8 bus;
1221 u8 slot;
1222 u8 path;
1223 struct list_head list;

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1261#define BP_ABS_FUNC(bp) (bp->pf_num)
1262#define BP_VN(bp) ((bp)->pfid >> 1)
1263#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1264#define BP_L_ID(bp) (BP_VN(bp) << 2)
1265#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1266 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1267#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1268
1269#ifdef CONFIG_BNX2X_SRIOV
1270 /* vf pf channel mailbox contains request and response buffers */
1271 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1272 dma_addr_t vf2pf_mbox_mapping;
1273
1274 /* we set aside a copy of the acquire response */
1275 struct pfvf_acquire_resp_tlv acquire_resp;
1276
1277 /* bulletin board for messages from pf to vf */
1278 union pf_vf_bulletin *pf2vf_bulletin;
1279 dma_addr_t pf2vf_bulletin_mapping;
1280
1281 struct pf_vf_bulletin_content old_bulletin;
1282#endif /* CONFIG_BNX2X_SRIOV */
1283
1234 struct net_device *dev;
1235 struct pci_dev *pdev;
1236
1237 const struct iro *iro_arr;
1238#define IRO (bp->iro_arr)
1239
1240 enum bnx2x_recovery_state recovery_state;
1241 int is_leader;

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1313#define ONE_PORT_FLAG (1 << 2)
1314#define NO_WOL_FLAG (1 << 3)
1315#define USING_DAC_FLAG (1 << 4)
1316#define USING_MSIX_FLAG (1 << 5)
1317#define USING_MSI_FLAG (1 << 6)
1318#define DISABLE_MSI_FLAG (1 << 7)
1319#define TPA_ENABLE_FLAG (1 << 8)
1320#define NO_MCP_FLAG (1 << 9)
1284 struct net_device *dev;
1285 struct pci_dev *pdev;
1286
1287 const struct iro *iro_arr;
1288#define IRO (bp->iro_arr)
1289
1290 enum bnx2x_recovery_state recovery_state;
1291 int is_leader;

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1363#define ONE_PORT_FLAG (1 << 2)
1364#define NO_WOL_FLAG (1 << 3)
1365#define USING_DAC_FLAG (1 << 4)
1366#define USING_MSIX_FLAG (1 << 5)
1367#define USING_MSI_FLAG (1 << 6)
1368#define DISABLE_MSI_FLAG (1 << 7)
1369#define TPA_ENABLE_FLAG (1 << 8)
1370#define NO_MCP_FLAG (1 << 9)
1321
1322#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1323#define GRO_ENABLE_FLAG (1 << 10)
1324#define MF_FUNC_DIS (1 << 11)
1325#define OWN_CNIC_IRQ (1 << 12)
1326#define NO_ISCSI_OOO_FLAG (1 << 13)
1327#define NO_ISCSI_FLAG (1 << 14)
1328#define NO_FCOE_FLAG (1 << 15)
1329#define BC_SUPPORTS_PFC_STATS (1 << 17)
1330#define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1331#define USING_SINGLE_MSIX_FLAG (1 << 20)
1332#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1371#define GRO_ENABLE_FLAG (1 << 10)
1372#define MF_FUNC_DIS (1 << 11)
1373#define OWN_CNIC_IRQ (1 << 12)
1374#define NO_ISCSI_OOO_FLAG (1 << 13)
1375#define NO_ISCSI_FLAG (1 << 14)
1376#define NO_FCOE_FLAG (1 << 15)
1377#define BC_SUPPORTS_PFC_STATS (1 << 17)
1378#define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1379#define USING_SINGLE_MSIX_FLAG (1 << 20)
1380#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1381#define IS_VF_FLAG (1 << 22)
1333
1382
1383#define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1384
1385#ifdef CONFIG_BNX2X_SRIOV
1386#define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1387#define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1388#else
1389#define IS_VF(bp) false
1390#define IS_PF(bp) true
1391#endif
1392
1334#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1335#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1336#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1337
1338 u8 cnic_support;
1339 bool cnic_enabled;
1340 bool cnic_loaded;
1341 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1342
1343 /* Flag that indicates that we can start looking for FCoE L2 queue
1344 * completions in the default status block.
1345 */
1346 bool fcoe_init;
1347
1348 int pm_cap;
1349 int mrrs;
1350
1351 struct delayed_work sp_task;
1393#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1394#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1395#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1396
1397 u8 cnic_support;
1398 bool cnic_enabled;
1399 bool cnic_loaded;
1400 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1401
1402 /* Flag that indicates that we can start looking for FCoE L2 queue
1403 * completions in the default status block.
1404 */
1405 bool fcoe_init;
1406
1407 int pm_cap;
1408 int mrrs;
1409
1410 struct delayed_work sp_task;
1411 atomic_t interrupt_occurred;
1352 struct delayed_work sp_rtnl_task;
1353
1354 struct delayed_work period_task;
1355 struct timer_list timer;
1356 int current_interval;
1357
1358 u16 fw_seq;
1359 u16 fw_drv_pulse_wr_seq;

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1427#define BNX2X_RX_MODE_PROMISC 3
1428#define BNX2X_MAX_MULTICAST 64
1429
1430 u8 igu_dsb_id;
1431 u8 igu_base_sb;
1432 u8 igu_sb_cnt;
1433 u8 min_msix_vec_cnt;
1434
1412 struct delayed_work sp_rtnl_task;
1413
1414 struct delayed_work period_task;
1415 struct timer_list timer;
1416 int current_interval;
1417
1418 u16 fw_seq;
1419 u16 fw_drv_pulse_wr_seq;

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1487#define BNX2X_RX_MODE_PROMISC 3
1488#define BNX2X_MAX_MULTICAST 64
1489
1490 u8 igu_dsb_id;
1491 u8 igu_base_sb;
1492 u8 igu_sb_cnt;
1493 u8 min_msix_vec_cnt;
1494
1495 u32 igu_base_addr;
1435 dma_addr_t def_status_blk_mapping;
1436
1437 struct bnx2x_slowpath *slowpath;
1438 dma_addr_t slowpath_mapping;
1439
1440 /* Total number of FW statistics requests */
1441 u8 fw_stats_num;
1442

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1575#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1576#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1577#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1578
1579#define PHY_FW_VER_LEN 20
1580 char fw_ver[32];
1581 const struct firmware *firmware;
1582
1496 dma_addr_t def_status_blk_mapping;
1497
1498 struct bnx2x_slowpath *slowpath;
1499 dma_addr_t slowpath_mapping;
1500
1501 /* Total number of FW statistics requests */
1502 u8 fw_stats_num;
1503

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1636#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1637#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1638#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1639
1640#define PHY_FW_VER_LEN 20
1641 char fw_ver[32];
1642 const struct firmware *firmware;
1643
1644 struct bnx2x_vfdb *vfdb;
1645#define IS_SRIOV(bp) ((bp)->vfdb)
1646
1583 /* DCB support on/off */
1584 u16 dcb_state;
1585#define BNX2X_DCB_STATE_OFF 0
1586#define BNX2X_DCB_STATE_ON 1
1587
1588 /* DCBX engine mode */
1589 int dcbx_enabled;
1590#define BNX2X_DCBX_ENABLED_OFF 0
1591#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1592#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1593#define BNX2X_DCBX_ENABLED_INVALID (-1)
1594
1595 bool dcbx_mode_uset;
1596
1597 struct bnx2x_config_dcbx_params dcbx_config_params;
1598 struct bnx2x_dcbx_port_params dcbx_port_params;
1599 int dcb_version;
1600
1601 /* CAM credit pools */
1647 /* DCB support on/off */
1648 u16 dcb_state;
1649#define BNX2X_DCB_STATE_OFF 0
1650#define BNX2X_DCB_STATE_ON 1
1651
1652 /* DCBX engine mode */
1653 int dcbx_enabled;
1654#define BNX2X_DCBX_ENABLED_OFF 0
1655#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1656#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1657#define BNX2X_DCBX_ENABLED_INVALID (-1)
1658
1659 bool dcbx_mode_uset;
1660
1661 struct bnx2x_config_dcbx_params dcbx_config_params;
1662 struct bnx2x_dcbx_port_params dcbx_port_params;
1663 int dcb_version;
1664
1665 /* CAM credit pools */
1666
1667 /* used only in sriov */
1668 struct bnx2x_credit_pool_obj vlans_pool;
1669
1602 struct bnx2x_credit_pool_obj macs_pool;
1603
1604 /* RX_MODE object */
1605 struct bnx2x_rx_mode_obj rx_mode_obj;
1606
1607 /* MCAST object */
1608 struct bnx2x_mcast_obj mcast_obj;
1609

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1808 * operations has failed.
1809 */
1810int bnx2x_del_all_macs(struct bnx2x *bp,
1811 struct bnx2x_vlan_mac_obj *mac_obj,
1812 int mac_type, bool wait_for_comp);
1813
1814/* Init Function API */
1815void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1670 struct bnx2x_credit_pool_obj macs_pool;
1671
1672 /* RX_MODE object */
1673 struct bnx2x_rx_mode_obj rx_mode_obj;
1674
1675 /* MCAST object */
1676 struct bnx2x_mcast_obj mcast_obj;
1677

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1876 * operations has failed.
1877 */
1878int bnx2x_del_all_macs(struct bnx2x *bp,
1879 struct bnx2x_vlan_mac_obj *mac_obj,
1880 int mac_type, bool wait_for_comp);
1881
1882/* Init Function API */
1883void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1884void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
1885 u8 vf_valid, int fw_sb_id, int igu_sb_id);
1886u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
1816int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1817int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1818int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1819int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1820void bnx2x_read_mf_cfg(struct bnx2x *bp);
1821
1887int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1888int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1889int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1890int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1891void bnx2x_read_mf_cfg(struct bnx2x *bp);
1892
1893int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
1822
1823/* dmae */
1824void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1825void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1826 u32 len32);
1827void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1828u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1829u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1830u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1831 bool with_comp, u8 comp_type);
1832
1894
1895/* dmae */
1896void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1897void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1898 u32 len32);
1899void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1900u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1901u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1902u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1903 bool with_comp, u8 comp_type);
1904
1905void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
1906 u8 src_type, u8 dst_type);
1907int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
1908void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl);
1833
1909
1910/* FLR related routines */
1911u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
1912void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
1913int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
1914u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
1915int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1916 char *msg, u32 poll_cnt);
1917
1834void bnx2x_calc_fc_adv(struct bnx2x *bp);
1835int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1836 u32 data_hi, u32 data_lo, int cmd_type);
1837void bnx2x_update_coalesce(struct bnx2x *bp);
1838int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1839
1840static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1841 int wait)

--- 7 unchanged lines hidden (view full) ---

1849 ms -= wait;
1850 msleep(wait);
1851
1852 } while (ms > 0);
1853
1854 return val;
1855}
1856
1918void bnx2x_calc_fc_adv(struct bnx2x *bp);
1919int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1920 u32 data_hi, u32 data_lo, int cmd_type);
1921void bnx2x_update_coalesce(struct bnx2x *bp);
1922int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1923
1924static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1925 int wait)

--- 7 unchanged lines hidden (view full) ---

1933 ms -= wait;
1934 msleep(wait);
1935
1936 } while (ms > 0);
1937
1938 return val;
1939}
1940
1941void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
1942 bool is_pf);
1943
1857#define BNX2X_ILT_ZALLOC(x, y, size) \
1858 do { \
1859 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1860 if (x) \
1861 memset(x, 0, size); \
1862 } while (0)
1863
1864#define BNX2X_ILT_FREE(x, y, size) \

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2185
2186#ifndef ETH_MAX_RX_CLIENTS_E2
2187#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2188#endif
2189
2190#define BNX2X_VPD_LEN 128
2191#define VENDOR_ID_LEN 4
2192
1944#define BNX2X_ILT_ZALLOC(x, y, size) \
1945 do { \
1946 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1947 if (x) \
1948 memset(x, 0, size); \
1949 } while (0)
1950
1951#define BNX2X_ILT_FREE(x, y, size) \

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2272
2273#ifndef ETH_MAX_RX_CLIENTS_E2
2274#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2275#endif
2276
2277#define BNX2X_VPD_LEN 128
2278#define VENDOR_ID_LEN 4
2279
2280#define VF_ACQUIRE_THRESH 3
2281#define VF_ACQUIRE_MAC_FILTERS 1
2282#define VF_ACQUIRE_MC_FILTERS 10
2283
2284#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2285 (!((me_reg) & ME_REG_VF_ERR)))
2286int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2193/* Congestion management fairness mode */
2194#define CMNG_FNS_NONE 0
2195#define CMNG_FNS_MINMAX 1
2196
2197#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2198#define HC_SEG_ACCESS_ATTN 4
2199#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2200

--- 39 unchanged lines hidden --- 		2287/* Congestion management fairness mode */
2288#define CMNG_FNS_NONE 0
2289#define CMNG_FNS_MINMAX 1
2290
2291#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2292#define HC_SEG_ACCESS_ATTN 4
2293#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2294

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