bnge.h (7037d1d8979653e4da384b732d2f38d151b9f493) bnge.h (fb7d8b61c1f77a5d47fc5cc057d6095acfbedd92)
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2025 Broadcom */
3
4#ifndef _BNGE_H_
5#define _BNGE_H_
6
7#define DRV_NAME "bng_en"
8#define DRV_SUMMARY "Broadcom 800G Ethernet Linux Driver"
9
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2025 Broadcom */
3
4#ifndef _BNGE_H_
5#define _BNGE_H_
6
7#define DRV_NAME "bng_en"
8#define DRV_SUMMARY "Broadcom 800G Ethernet Linux Driver"
9
10#include <linux/etherdevice.h>
11#include "../bnxt/bnxt_hsi.h"
12
13#define DRV_VER_MAJ 1
14#define DRV_VER_MIN 15
15#define DRV_VER_UPD 1
16
10extern char bnge_driver_name[];
11
12enum board_idx {
13 BCM57708,
14};
15
16#define INVALID_HW_RING_ID ((u16)-1)
17
17extern char bnge_driver_name[];
18
19enum board_idx {
20 BCM57708,
21};
22
23#define INVALID_HW_RING_ID ((u16)-1)
24
25enum {
26 BNGE_FW_CAP_SHORT_CMD = BIT_ULL(0),
27 BNGE_FW_CAP_LLDP_AGENT = BIT_ULL(1),
28 BNGE_FW_CAP_DCBX_AGENT = BIT_ULL(2),
29 BNGE_FW_CAP_IF_CHANGE = BIT_ULL(3),
30 BNGE_FW_CAP_KONG_MB_CHNL = BIT_ULL(4),
31 BNGE_FW_CAP_ERROR_RECOVERY = BIT_ULL(5),
32 BNGE_FW_CAP_PKG_VER = BIT_ULL(6),
33 BNGE_FW_CAP_CFA_ADV_FLOW = BIT_ULL(7),
34 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 = BIT_ULL(8),
35 BNGE_FW_CAP_PCIE_STATS_SUPPORTED = BIT_ULL(9),
36 BNGE_FW_CAP_EXT_STATS_SUPPORTED = BIT_ULL(10),
37 BNGE_FW_CAP_ERR_RECOVER_RELOAD = BIT_ULL(11),
38 BNGE_FW_CAP_HOT_RESET = BIT_ULL(12),
39 BNGE_FW_CAP_RX_ALL_PKT_TS = BIT_ULL(13),
40 BNGE_FW_CAP_VLAN_RX_STRIP = BIT_ULL(14),
41 BNGE_FW_CAP_VLAN_TX_INSERT = BIT_ULL(15),
42 BNGE_FW_CAP_EXT_HW_STATS_SUPPORTED = BIT_ULL(16),
43 BNGE_FW_CAP_LIVEPATCH = BIT_ULL(17),
44 BNGE_FW_CAP_HOT_RESET_IF = BIT_ULL(18),
45 BNGE_FW_CAP_RING_MONITOR = BIT_ULL(19),
46 BNGE_FW_CAP_DBG_QCAPS = BIT_ULL(20),
47 BNGE_FW_CAP_THRESHOLD_TEMP_SUPPORTED = BIT_ULL(21),
48 BNGE_FW_CAP_DFLT_VLAN_TPID_PCP = BIT_ULL(22),
49 BNGE_FW_CAP_VNIC_TUNNEL_TPA = BIT_ULL(23),
50 BNGE_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO = BIT_ULL(24),
51 BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V3 = BIT_ULL(25),
52 BNGE_FW_CAP_VNIC_RE_FLUSH = BIT_ULL(26),
53};
54
18struct bnge_dev {
19 struct device *dev;
20 struct pci_dev *pdev;
21 u64 dsn;
22#define BNGE_VPD_FLD_LEN 32
23 char board_partno[BNGE_VPD_FLD_LEN];
24 char board_serialno[BNGE_VPD_FLD_LEN];
25
26 void __iomem *bar0;
27
55struct bnge_dev {
56 struct device *dev;
57 struct pci_dev *pdev;
58 u64 dsn;
59#define BNGE_VPD_FLD_LEN 32
60 char board_partno[BNGE_VPD_FLD_LEN];
61 char board_serialno[BNGE_VPD_FLD_LEN];
62
63 void __iomem *bar0;
64
65 u16 chip_num;
66 u8 chip_rev;
67
28 /* HWRM members */
29 u16 hwrm_cmd_seq;
30 u16 hwrm_cmd_kong_seq;
31 struct dma_pool *hwrm_dma_pool;
32 struct hlist_head hwrm_pending_list;
33 u16 hwrm_max_req_len;
34 u16 hwrm_max_ext_req_len;
35 unsigned int hwrm_cmd_timeout;
36 unsigned int hwrm_cmd_max_timeout;
37 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
68 /* HWRM members */
69 u16 hwrm_cmd_seq;
70 u16 hwrm_cmd_kong_seq;
71 struct dma_pool *hwrm_dma_pool;
72 struct hlist_head hwrm_pending_list;
73 u16 hwrm_max_req_len;
74 u16 hwrm_max_ext_req_len;
75 unsigned int hwrm_cmd_timeout;
76 unsigned int hwrm_cmd_max_timeout;
77 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
78
79 struct hwrm_ver_get_output ver_resp;
80#define FW_VER_STR_LEN 32
81 char fw_ver_str[FW_VER_STR_LEN];
82 char hwrm_ver_supp[FW_VER_STR_LEN];
83 char nvm_cfg_ver[FW_VER_STR_LEN];
84 u64 fw_ver_code;
85#define BNGE_FW_VER_CODE(maj, min, bld, rsv) \
86 ((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
87
88 unsigned long state;
89#define BNGE_STATE_DRV_REGISTERED 0
90
91 u64 fw_cap;
38};
39
40#endif /* _BNGE_H_ */
92};
93
94#endif /* _BNGE_H_ */