chip.c (ca09fb9f60b5f3ab2d57e761aaeea89a5147d784) chip.c (a935c0523c852feb619a050597bb545e7c818d81)
1/*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *

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24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/of_mdio.h>
27#include <linux/netdevice.h>
28#include <linux/gpio/consumer.h>
29#include <linux/phy.h>
30#include <net/dsa.h>
31#include <net/switchdev.h>
1/*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *

--- 15 unchanged lines hidden (view full) ---

24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/of_mdio.h>
27#include <linux/netdevice.h>
28#include <linux/gpio/consumer.h>
29#include <linux/phy.h>
30#include <net/dsa.h>
31#include <net/switchdev.h>
32
32#include "mv88e6xxx.h"
33#include "mv88e6xxx.h"
34#include "global1.h"
35#include "global2.h"
33
34static void assert_reg_lock(struct mv88e6xxx_chip *chip)
35{
36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
38 dump_stack();
39 }
40}

--- 136 unchanged lines hidden (view full) ---

177 return 0;
178}
179
180static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
183};
184
36
37static void assert_reg_lock(struct mv88e6xxx_chip *chip)
38{
39 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
40 dev_err(chip->dev, "Switch registers lock not held!\n");
41 dump_stack();
42 }
43}

--- 136 unchanged lines hidden (view full) ---

180 return 0;
181}
182
183static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
184 .read = mv88e6xxx_smi_multi_chip_read,
185 .write = mv88e6xxx_smi_multi_chip_write,
186};
187
185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
186 int addr, int reg, u16 *val)
188int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
187{
188 int err;
189
190 assert_reg_lock(chip);
191
192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
193 if (err)
194 return err;
195
196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
197 addr, reg, *val);
198
199 return 0;
200}
201
189{
190 int err;
191
192 assert_reg_lock(chip);
193
194 err = mv88e6xxx_smi_read(chip, addr, reg, val);
195 if (err)
196 return err;
197
198 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
199 addr, reg, *val);
200
201 return 0;
202}
203
202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
203 int addr, int reg, u16 val)
204int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
204{
205 int err;
206
207 assert_reg_lock(chip);
208
209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
210 if (err)
211 return err;
212
213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
214 addr, reg, val);
215
216 return 0;
217}
218
205{
206 int err;
207
208 assert_reg_lock(chip);
209
210 err = mv88e6xxx_smi_write(chip, addr, reg, val);
211 if (err)
212 return err;
213
214 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
215 addr, reg, val);
216
217 return 0;
218}
219
219/* Indirect write to single pointer-data register with an Update bit */
220static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
221 u16 update)
220static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
221 u16 *val)
222{
222{
223 u16 val;
224 int i, err;
223 int addr = chip->info->port_base_addr + port;
225
224
226 /* Wait until the previous operation is completed */
227 for (i = 0; i < 16; ++i) {
228 err = mv88e6xxx_read(chip, addr, reg, &val);
229 if (err)
230 return err;
225 return mv88e6xxx_read(chip, addr, reg, val);
226}
231
227
232 if (!(val & BIT(15)))
233 break;
228static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
229 u16 val)
230{
231 int addr = chip->info->port_base_addr + port;
232
233 return mv88e6xxx_write(chip, addr, reg, val);
234}
235
236static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 *val)
238{
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
241 if (!chip->phy_ops)
242 return -EOPNOTSUPP;
243
244 return chip->phy_ops->read(chip, addr, reg, val);
245}
246
247static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
248 int reg, u16 val)
249{
250 int addr = phy; /* PHY devices addresses start at 0x0 */
251
252 if (!chip->phy_ops)
253 return -EOPNOTSUPP;
254
255 return chip->phy_ops->write(chip, addr, reg, val);
256}
257
258static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
259{
260 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
261 return -EOPNOTSUPP;
262
263 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
264}
265
266static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
267{
268 int err;
269
270 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
271 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
272 if (unlikely(err)) {
273 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
274 phy, err);
234 }
275 }
276}
235
277
236 if (i == 16)
237 return -ETIMEDOUT;
278static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
279 u8 page, int reg, u16 *val)
280{
281 int err;
238
282
239 /* Set the Update bit to trigger a write operation */
240 val = BIT(15) | update;
283 /* There is no paging for registers 22 */
284 if (reg == PHY_PAGE)
285 return -EINVAL;
241
286
242 return mv88e6xxx_write(chip, addr, reg, val);
287 err = mv88e6xxx_phy_page_get(chip, phy, page);
288 if (!err) {
289 err = mv88e6xxx_phy_read(chip, phy, reg, val);
290 mv88e6xxx_phy_page_put(chip, phy);
291 }
292
293 return err;
243}
244
294}
295
245static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
296static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
297 u8 page, int reg, u16 val)
246{
298{
247 u16 val;
248 int err;
249
299 int err;
300
250 err = mv88e6xxx_read(chip, addr, reg, &val);
251 if (err)
252 return err;
301 /* There is no paging for registers 22 */
302 if (reg == PHY_PAGE)
303 return -EINVAL;
253
304
254 return val;
305 err = mv88e6xxx_phy_page_get(chip, phy, page);
306 if (!err) {
307 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
308 mv88e6xxx_phy_page_put(chip, phy);
309 }
310
311 return err;
255}
256
312}
313
257static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
258 int reg, u16 val)
314static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
259{
315{
260 return mv88e6xxx_write(chip, addr, reg, val);
316 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
317 reg, val);
261}
262
318}
319
263static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
264 int addr, int regnum)
320static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
265{
321{
266 if (addr >= 0)
267 return _mv88e6xxx_reg_read(chip, addr, regnum);
268 return 0xffff;
322 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
323 reg, val);
269}
270
324}
325
271static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
272 int addr, int regnum, u16 val)
326int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
273{
327{
274 if (addr >= 0)
275 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
276 return 0;
328 int i;
329
330 for (i = 0; i < 16; i++) {
331 u16 val;
332 int err;
333
334 err = mv88e6xxx_read(chip, addr, reg, &val);
335 if (err)
336 return err;
337
338 if (!(val & mask))
339 return 0;
340
341 usleep_range(1000, 2000);
342 }
343
344 dev_err(chip->dev, "Timeout while waiting for switch\n");
345 return -ETIMEDOUT;
277}
278
346}
347
348/* Indirect write to single pointer-data register with an Update bit */
349int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
350{
351 u16 val;
352 int err;
353
354 /* Wait until the previous operation is completed */
355 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
356 if (err)
357 return err;
358
359 /* Set the Update bit to trigger a write operation */
360 val = BIT(15) | update;
361
362 return mv88e6xxx_write(chip, addr, reg, val);
363}
364
279static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
280{
365static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
366{
281 int ret;
282 unsigned long timeout;
367 u16 val;
368 int i, err;
283
369
284 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
285 if (ret < 0)
286 return ret;
370 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
371 if (err)
372 return err;
287
373
288 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
289 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
290 if (ret)
291 return ret;
374 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
375 val & ~GLOBAL_CONTROL_PPU_ENABLE);
376 if (err)
377 return err;
292
378
293 timeout = jiffies + 1 * HZ;
294 while (time_before(jiffies, timeout)) {
295 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
296 if (ret < 0)
297 return ret;
379 for (i = 0; i < 16; i++) {
380 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
381 if (err)
382 return err;
298
299 usleep_range(1000, 2000);
383
384 usleep_range(1000, 2000);
300 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
301 GLOBAL_STATUS_PPU_POLLING)
385 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
302 return 0;
303 }
304
305 return -ETIMEDOUT;
306}
307
308static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
309{
386 return 0;
387 }
388
389 return -ETIMEDOUT;
390}
391
392static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
393{
310 int ret, err;
311 unsigned long timeout;
394 u16 val;
395 int i, err;
312
396
313 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
314 if (ret < 0)
315 return ret;
397 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
398 if (err)
399 return err;
316
400
317 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
318 ret | GLOBAL_CONTROL_PPU_ENABLE);
401 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
402 val | GLOBAL_CONTROL_PPU_ENABLE);
319 if (err)
320 return err;
321
403 if (err)
404 return err;
405
322 timeout = jiffies + 1 * HZ;
323 while (time_before(jiffies, timeout)) {
324 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
325 if (ret < 0)
326 return ret;
406 for (i = 0; i < 16; i++) {
407 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
408 if (err)
409 return err;
327
328 usleep_range(1000, 2000);
410
411 usleep_range(1000, 2000);
329 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
330 GLOBAL_STATUS_PPU_POLLING)
412 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
331 return 0;
332 }
333
334 return -ETIMEDOUT;
335}
336
337static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
338{

--- 56 unchanged lines hidden (view full) ---

395{
396 mutex_init(&chip->ppu_mutex);
397 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
398 init_timer(&chip->ppu_timer);
399 chip->ppu_timer.data = (unsigned long)chip;
400 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
401}
402
413 return 0;
414 }
415
416 return -ETIMEDOUT;
417}
418
419static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
420{

--- 56 unchanged lines hidden (view full) ---

477{
478 mutex_init(&chip->ppu_mutex);
479 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
480 init_timer(&chip->ppu_timer);
481 chip->ppu_timer.data = (unsigned long)chip;
482 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
483}
484
403static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
404 int regnum)
485static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
405{
486{
406 int ret;
487 del_timer_sync(&chip->ppu_timer);
488}
407
489
408 ret = mv88e6xxx_ppu_access_get(chip);
409 if (ret >= 0) {
410 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
490static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
491 int reg, u16 *val)
492{
493 int err;
494
495 err = mv88e6xxx_ppu_access_get(chip);
496 if (!err) {
497 err = mv88e6xxx_read(chip, addr, reg, val);
411 mv88e6xxx_ppu_access_put(chip);
412 }
413
498 mv88e6xxx_ppu_access_put(chip);
499 }
500
414 return ret;
501 return err;
415}
416
502}
503
417static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
418 int regnum, u16 val)
504static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
505 int reg, u16 val)
419{
506{
420 int ret;
507 int err;
421
508
422 ret = mv88e6xxx_ppu_access_get(chip);
423 if (ret >= 0) {
424 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
509 err = mv88e6xxx_ppu_access_get(chip);
510 if (!err) {
511 err = mv88e6xxx_write(chip, addr, reg, val);
425 mv88e6xxx_ppu_access_put(chip);
426 }
427
512 mv88e6xxx_ppu_access_put(chip);
513 }
514
428 return ret;
515 return err;
429}
430
516}
517
518static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
519 .read = mv88e6xxx_phy_ppu_read,
520 .write = mv88e6xxx_phy_ppu_write,
521};
522
431static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
432{
433 return chip->info->family == MV88E6XXX_FAMILY_6065;
434}
435
436static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
437{
438 return chip->info->family == MV88E6XXX_FAMILY_6095;

--- 46 unchanged lines hidden (view full) ---

485
486/* We expect the switch to perform auto negotiation if there is a real
487 * phy. However, in the case of a fixed link phy, we force the port
488 * settings from the fixed link settings.
489 */
490static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
491 struct phy_device *phydev)
492{
523static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
524{
525 return chip->info->family == MV88E6XXX_FAMILY_6065;
526}
527
528static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
529{
530 return chip->info->family == MV88E6XXX_FAMILY_6095;

--- 46 unchanged lines hidden (view full) ---

577
578/* We expect the switch to perform auto negotiation if there is a real
579 * phy. However, in the case of a fixed link phy, we force the port
580 * settings from the fixed link settings.
581 */
582static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
583 struct phy_device *phydev)
584{
493 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
494 u32 reg;
495 int ret;
585 struct mv88e6xxx_chip *chip = ds->priv;
586 u16 reg;
587 int err;
496
497 if (!phy_is_pseudo_fixed_link(phydev))
498 return;
499
500 mutex_lock(&chip->reg_lock);
501
588
589 if (!phy_is_pseudo_fixed_link(phydev))
590 return;
591
592 mutex_lock(&chip->reg_lock);
593
502 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
503 if (ret < 0)
594 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
595 if (err)
504 goto out;
505
596 goto out;
597
506 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
507 PORT_PCS_CTRL_FORCE_LINK |
508 PORT_PCS_CTRL_DUPLEX_FULL |
509 PORT_PCS_CTRL_FORCE_DUPLEX |
510 PORT_PCS_CTRL_UNFORCED);
598 reg &= ~(PORT_PCS_CTRL_LINK_UP |
599 PORT_PCS_CTRL_FORCE_LINK |
600 PORT_PCS_CTRL_DUPLEX_FULL |
601 PORT_PCS_CTRL_FORCE_DUPLEX |
602 PORT_PCS_CTRL_UNFORCED);
511
512 reg |= PORT_PCS_CTRL_FORCE_LINK;
513 if (phydev->link)
514 reg |= PORT_PCS_CTRL_LINK_UP;
515
516 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
517 goto out;
518

--- 21 unchanged lines hidden (view full) ---

540 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
541 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
542 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
543 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
544 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
545 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
546 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
547 }
603
604 reg |= PORT_PCS_CTRL_FORCE_LINK;
605 if (phydev->link)
606 reg |= PORT_PCS_CTRL_LINK_UP;
607
608 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
609 goto out;
610

--- 21 unchanged lines hidden (view full) ---

632 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
633 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
634 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
635 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
636 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
637 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
638 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
639 }
548 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
640 mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
549
550out:
551 mutex_unlock(&chip->reg_lock);
552}
553
554static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
555{
641
642out:
643 mutex_unlock(&chip->reg_lock);
644}
645
646static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
647{
556 int ret;
557 int i;
648 u16 val;
649 int i, err;
558
559 for (i = 0; i < 10; i++) {
650
651 for (i = 0; i < 10; i++) {
560 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
561 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
652 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val);
653 if ((val & GLOBAL_STATS_OP_BUSY) == 0)
562 return 0;
563 }
564
565 return -ETIMEDOUT;
566}
567
568static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
569{
654 return 0;
655 }
656
657 return -ETIMEDOUT;
658}
659
660static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
661{
570 int ret;
662 int err;
571
572 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
573 port = (port + 1) << 5;
574
575 /* Snapshot the hardware statistics counters for this port. */
663
664 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
665 port = (port + 1) << 5;
666
667 /* Snapshot the hardware statistics counters for this port. */
576 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
577 GLOBAL_STATS_OP_CAPTURE_PORT |
578 GLOBAL_STATS_OP_HIST_RX_TX | port);
579 if (ret < 0)
580 return ret;
668 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
669 GLOBAL_STATS_OP_CAPTURE_PORT |
670 GLOBAL_STATS_OP_HIST_RX_TX | port);
671 if (err)
672 return err;
581
582 /* Wait for the snapshotting to complete. */
673
674 /* Wait for the snapshotting to complete. */
583 ret = _mv88e6xxx_stats_wait(chip);
584 if (ret < 0)
585 return ret;
586
587 return 0;
675 return _mv88e6xxx_stats_wait(chip);
588}
589
590static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
591 int stat, u32 *val)
592{
676}
677
678static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
679 int stat, u32 *val)
680{
593 u32 _val;
594 int ret;
681 u32 value;
682 u16 reg;
683 int err;
595
596 *val = 0;
597
684
685 *val = 0;
686
598 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
599 GLOBAL_STATS_OP_READ_CAPTURED |
600 GLOBAL_STATS_OP_HIST_RX_TX | stat);
601 if (ret < 0)
687 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
688 GLOBAL_STATS_OP_READ_CAPTURED |
689 GLOBAL_STATS_OP_HIST_RX_TX | stat);
690 if (err)
602 return;
603
691 return;
692
604 ret = _mv88e6xxx_stats_wait(chip);
605 if (ret < 0)
693 err = _mv88e6xxx_stats_wait(chip);
694 if (err)
606 return;
607
695 return;
696
608 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
609 if (ret < 0)
697 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, &reg);
698 if (err)
610 return;
611
699 return;
700
612 _val = ret << 16;
701 value = reg << 16;
613
702
614 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
615 if (ret < 0)
703 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, &reg);
704 if (err)
616 return;
617
705 return;
706
618 *val = _val | ret;
707 *val = value | reg;
619}
620
621static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
622 { "in_good_octets", 8, 0x00, BANK0, },
623 { "in_bad_octets", 4, 0x02, BANK0, },
624 { "in_unicast", 4, 0x04, BANK0, },
625 { "in_broadcasts", 4, 0x06, BANK0, },
626 { "in_multicasts", 4, 0x07, BANK0, },

--- 73 unchanged lines hidden (view full) ---

700}
701
702static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
703 struct mv88e6xxx_hw_stat *s,
704 int port)
705{
706 u32 low;
707 u32 high = 0;
708}
709
710static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
711 { "in_good_octets", 8, 0x00, BANK0, },
712 { "in_bad_octets", 4, 0x02, BANK0, },
713 { "in_unicast", 4, 0x04, BANK0, },
714 { "in_broadcasts", 4, 0x06, BANK0, },
715 { "in_multicasts", 4, 0x07, BANK0, },

--- 73 unchanged lines hidden (view full) ---

789}
790
791static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
792 struct mv88e6xxx_hw_stat *s,
793 int port)
794{
795 u32 low;
796 u32 high = 0;
708 int ret;
797 int err;
798 u16 reg;
709 u64 value;
710
711 switch (s->type) {
712 case PORT:
799 u64 value;
800
801 switch (s->type) {
802 case PORT:
713 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
714 if (ret < 0)
803 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
804 if (err)
715 return UINT64_MAX;
716
805 return UINT64_MAX;
806
717 low = ret;
807 low = reg;
718 if (s->sizeof_stat == 4) {
808 if (s->sizeof_stat == 4) {
719 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
720 s->reg + 1);
721 if (ret < 0)
809 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
810 if (err)
722 return UINT64_MAX;
811 return UINT64_MAX;
723 high = ret;
812 high = reg;
724 }
725 break;
726 case BANK0:
727 case BANK1:
728 _mv88e6xxx_stats_read(chip, s->reg, &low);
729 if (s->sizeof_stat == 8)
730 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
731 }
732 value = (((u64)high) << 16) | low;
733 return value;
734}
735
736static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
737 uint8_t *data)
738{
813 }
814 break;
815 case BANK0:
816 case BANK1:
817 _mv88e6xxx_stats_read(chip, s->reg, &low);
818 if (s->sizeof_stat == 8)
819 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
820 }
821 value = (((u64)high) << 16) | low;
822 return value;
823}
824
825static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
826 uint8_t *data)
827{
739 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
828 struct mv88e6xxx_chip *chip = ds->priv;
740 struct mv88e6xxx_hw_stat *stat;
741 int i, j;
742
743 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
744 stat = &mv88e6xxx_hw_stats[i];
745 if (mv88e6xxx_has_stat(chip, stat)) {
746 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
747 ETH_GSTRING_LEN);
748 j++;
749 }
750 }
751}
752
753static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
754{
829 struct mv88e6xxx_hw_stat *stat;
830 int i, j;
831
832 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
833 stat = &mv88e6xxx_hw_stats[i];
834 if (mv88e6xxx_has_stat(chip, stat)) {
835 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
836 ETH_GSTRING_LEN);
837 j++;
838 }
839 }
840}
841
842static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
843{
755 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
844 struct mv88e6xxx_chip *chip = ds->priv;
756 struct mv88e6xxx_hw_stat *stat;
757 int i, j;
758
759 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
760 stat = &mv88e6xxx_hw_stats[i];
761 if (mv88e6xxx_has_stat(chip, stat))
762 j++;
763 }
764 return j;
765}
766
767static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
768 uint64_t *data)
769{
845 struct mv88e6xxx_hw_stat *stat;
846 int i, j;
847
848 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
849 stat = &mv88e6xxx_hw_stats[i];
850 if (mv88e6xxx_has_stat(chip, stat))
851 j++;
852 }
853 return j;
854}
855
856static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
857 uint64_t *data)
858{
770 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
859 struct mv88e6xxx_chip *chip = ds->priv;
771 struct mv88e6xxx_hw_stat *stat;
772 int ret;
773 int i, j;
774
775 mutex_lock(&chip->reg_lock);
776
777 ret = _mv88e6xxx_stats_snapshot(chip, port);
778 if (ret < 0) {

--- 14 unchanged lines hidden (view full) ---

793static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
794{
795 return 32 * sizeof(u16);
796}
797
798static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
799 struct ethtool_regs *regs, void *_p)
800{
860 struct mv88e6xxx_hw_stat *stat;
861 int ret;
862 int i, j;
863
864 mutex_lock(&chip->reg_lock);
865
866 ret = _mv88e6xxx_stats_snapshot(chip, port);
867 if (ret < 0) {

--- 14 unchanged lines hidden (view full) ---

882static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
883{
884 return 32 * sizeof(u16);
885}
886
887static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
888 struct ethtool_regs *regs, void *_p)
889{
801 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
890 struct mv88e6xxx_chip *chip = ds->priv;
891 int err;
892 u16 reg;
802 u16 *p = _p;
803 int i;
804
805 regs->version = 0;
806
807 memset(p, 0xff, 32 * sizeof(u16));
808
809 mutex_lock(&chip->reg_lock);
810
811 for (i = 0; i < 32; i++) {
893 u16 *p = _p;
894 int i;
895
896 regs->version = 0;
897
898 memset(p, 0xff, 32 * sizeof(u16));
899
900 mutex_lock(&chip->reg_lock);
901
902 for (i = 0; i < 32; i++) {
812 int ret;
813
903
814 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
815 if (ret >= 0)
816 p[i] = ret;
904 err = mv88e6xxx_port_read(chip, port, i, &reg);
905 if (!err)
906 p[i] = reg;
817 }
818
819 mutex_unlock(&chip->reg_lock);
820}
821
907 }
908
909 mutex_unlock(&chip->reg_lock);
910}
911
822static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
823 u16 mask)
824{
825 unsigned long timeout = jiffies + HZ / 10;
826
827 while (time_before(jiffies, timeout)) {
828 int ret;
829
830 ret = _mv88e6xxx_reg_read(chip, reg, offset);
831 if (ret < 0)
832 return ret;
833 if (!(ret & mask))
834 return 0;
835
836 usleep_range(1000, 2000);
837 }
838 return -ETIMEDOUT;
839}
840
841static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
842{
843 return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
844 GLOBAL2_SMI_OP_BUSY);
845}
846
847static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
848{
912static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
913{
849 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
850 GLOBAL_ATU_OP_BUSY);
914 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
851}
852
915}
916
853static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
854 int addr, int regnum)
855{
856 int ret;
857
858 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
859 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
860 regnum);
861 if (ret < 0)
862 return ret;
863
864 ret = mv88e6xxx_mdio_wait(chip);
865 if (ret < 0)
866 return ret;
867
868 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
869
870 return ret;
871}
872
873static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
874 int addr, int regnum, u16 val)
875{
876 int ret;
877
878 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
879 if (ret < 0)
880 return ret;
881
882 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
883 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
884 regnum);
885
886 return mv88e6xxx_mdio_wait(chip);
887}
888
889static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
890 struct ethtool_eee *e)
891{
917static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
918 struct ethtool_eee *e)
919{
892 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
893 int reg;
920 struct mv88e6xxx_chip *chip = ds->priv;
921 u16 reg;
922 int err;
894
895 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
896 return -EOPNOTSUPP;
897
898 mutex_lock(&chip->reg_lock);
899
923
924 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
925 return -EOPNOTSUPP;
926
927 mutex_lock(&chip->reg_lock);
928
900 reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
901 if (reg < 0)
929 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
930 if (err)
902 goto out;
903
904 e->eee_enabled = !!(reg & 0x0200);
905 e->tx_lpi_enabled = !!(reg & 0x0100);
906
931 goto out;
932
933 e->eee_enabled = !!(reg & 0x0200);
934 e->tx_lpi_enabled = !!(reg & 0x0100);
935
907 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
908 if (reg < 0)
936 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
937 if (err)
909 goto out;
910
911 e->eee_active = !!(reg & PORT_STATUS_EEE);
938 goto out;
939
940 e->eee_active = !!(reg & PORT_STATUS_EEE);
912 reg = 0;
913
914out:
915 mutex_unlock(&chip->reg_lock);
941out:
942 mutex_unlock(&chip->reg_lock);
916 return reg;
943
944 return err;
917}
918
919static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
920 struct phy_device *phydev, struct ethtool_eee *e)
921{
945}
946
947static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
948 struct phy_device *phydev, struct ethtool_eee *e)
949{
922 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
923 int reg;
924 int ret;
950 struct mv88e6xxx_chip *chip = ds->priv;
951 u16 reg;
952 int err;
925
926 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
927 return -EOPNOTSUPP;
928
929 mutex_lock(&chip->reg_lock);
930
953
954 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
955 return -EOPNOTSUPP;
956
957 mutex_lock(&chip->reg_lock);
958
931 ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
932 if (ret < 0)
959 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
960 if (err)
933 goto out;
934
961 goto out;
962
935 reg = ret & ~0x0300;
963 reg &= ~0x0300;
936 if (e->eee_enabled)
937 reg |= 0x0200;
938 if (e->tx_lpi_enabled)
939 reg |= 0x0100;
940
964 if (e->eee_enabled)
965 reg |= 0x0200;
966 if (e->tx_lpi_enabled)
967 reg |= 0x0100;
968
941 ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
969 err = mv88e6xxx_phy_write(chip, port, 16, reg);
942out:
943 mutex_unlock(&chip->reg_lock);
944
970out:
971 mutex_unlock(&chip->reg_lock);
972
945 return ret;
973 return err;
946}
947
948static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
949{
974}
975
976static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
977{
950 int ret;
978 u16 val;
979 int err;
951
952 if (mv88e6xxx_has_fid_reg(chip)) {
980
981 if (mv88e6xxx_has_fid_reg(chip)) {
953 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
954 fid);
955 if (ret < 0)
956 return ret;
982 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
983 if (err)
984 return err;
957 } else if (mv88e6xxx_num_databases(chip) == 256) {
958 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
985 } else if (mv88e6xxx_num_databases(chip) == 256) {
986 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
959 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
960 if (ret < 0)
961 return ret;
987 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
988 if (err)
989 return err;
962
990
963 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
964 (ret & 0xfff) |
965 ((fid << 8) & 0xf000));
966 if (ret < 0)
967 return ret;
991 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
992 (val & 0xfff) | ((fid << 8) & 0xf000));
993 if (err)
994 return err;
968
969 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
970 cmd |= fid & 0xf;
971 }
972
995
996 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
997 cmd |= fid & 0xf;
998 }
999
973 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
974 if (ret < 0)
975 return ret;
1000 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1001 if (err)
1002 return err;
976
977 return _mv88e6xxx_atu_wait(chip);
978}
979
980static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
981 struct mv88e6xxx_atu_entry *entry)
982{
983 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;

--- 8 unchanged lines hidden (view full) ---

992 } else {
993 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
994 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
995 }
996
997 data |= (entry->portv_trunkid << shift) & mask;
998 }
999
1003
1004 return _mv88e6xxx_atu_wait(chip);
1005}
1006
1007static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1008 struct mv88e6xxx_atu_entry *entry)
1009{
1010 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;

--- 8 unchanged lines hidden (view full) ---

1019 } else {
1020 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1021 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1022 }
1023
1024 data |= (entry->portv_trunkid << shift) & mask;
1025 }
1026
1000 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1027 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1001}
1002
1003static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1004 struct mv88e6xxx_atu_entry *entry,
1005 bool static_too)
1006{
1007 int op;
1008 int err;

--- 59 unchanged lines hidden (view full) ---

1068 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1069 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1070};
1071
1072static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1073 u8 state)
1074{
1075 struct dsa_switch *ds = chip->ds;
1028}
1029
1030static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1031 struct mv88e6xxx_atu_entry *entry,
1032 bool static_too)
1033{
1034 int op;
1035 int err;

--- 59 unchanged lines hidden (view full) ---

1095 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1096 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1097};
1098
1099static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1100 u8 state)
1101{
1102 struct dsa_switch *ds = chip->ds;
1076 int reg, ret = 0;
1103 u16 reg;
1104 int err;
1077 u8 oldstate;
1078
1105 u8 oldstate;
1106
1079 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1080 if (reg < 0)
1081 return reg;
1107 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, &reg);
1108 if (err)
1109 return err;
1082
1083 oldstate = reg & PORT_CONTROL_STATE_MASK;
1084
1110
1111 oldstate = reg & PORT_CONTROL_STATE_MASK;
1112
1085 if (oldstate != state) {
1086 /* Flush forwarding database if we're moving a port
1087 * from Learning or Forwarding state to Disabled or
1088 * Blocking or Listening state.
1089 */
1090 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1091 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1092 (state == PORT_CONTROL_STATE_DISABLED ||
1093 state == PORT_CONTROL_STATE_BLOCKING)) {
1094 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1095 if (ret)
1096 return ret;
1097 }
1113 reg &= ~PORT_CONTROL_STATE_MASK;
1114 reg |= state;
1098
1115
1099 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1100 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1101 reg);
1102 if (ret)
1103 return ret;
1116 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
1117 if (err)
1118 return err;
1104
1119
1105 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1106 mv88e6xxx_port_state_names[state],
1107 mv88e6xxx_port_state_names[oldstate]);
1108 }
1120 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1121 mv88e6xxx_port_state_names[state],
1122 mv88e6xxx_port_state_names[oldstate]);
1109
1123
1110 return ret;
1124 return 0;
1111}
1112
1113static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1114{
1115 struct net_device *bridge = chip->ports[port].bridge_dev;
1116 const u16 mask = (1 << chip->info->num_ports) - 1;
1117 struct dsa_switch *ds = chip->ds;
1118 u16 output_ports = 0;
1125}
1126
1127static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1128{
1129 struct net_device *bridge = chip->ports[port].bridge_dev;
1130 const u16 mask = (1 << chip->info->num_ports) - 1;
1131 struct dsa_switch *ds = chip->ds;
1132 u16 output_ports = 0;
1119 int reg;
1133 u16 reg;
1134 int err;
1120 int i;
1121
1122 /* allow CPU port or DSA link(s) to send frames to every port */
1123 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1124 output_ports = mask;
1125 } else {
1126 for (i = 0; i < chip->info->num_ports; ++i) {
1127 /* allow sending frames to every group member */

--- 4 unchanged lines hidden (view full) ---

1132 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1133 output_ports |= BIT(i);
1134 }
1135 }
1136
1137 /* prevent frames from going back out of the port they came in on */
1138 output_ports &= ~BIT(port);
1139
1135 int i;
1136
1137 /* allow CPU port or DSA link(s) to send frames to every port */
1138 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1139 output_ports = mask;
1140 } else {
1141 for (i = 0; i < chip->info->num_ports; ++i) {
1142 /* allow sending frames to every group member */

--- 4 unchanged lines hidden (view full) ---

1147 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1148 output_ports |= BIT(i);
1149 }
1150 }
1151
1152 /* prevent frames from going back out of the port they came in on */
1153 output_ports &= ~BIT(port);
1154
1140 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1141 if (reg < 0)
1142 return reg;
1155 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1156 if (err)
1157 return err;
1143
1144 reg &= ~mask;
1145 reg |= output_ports & mask;
1146
1158
1159 reg &= ~mask;
1160 reg |= output_ports & mask;
1161
1147 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1162 return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1148}
1149
1150static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1151 u8 state)
1152{
1163}
1164
1165static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1166 u8 state)
1167{
1153 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1168 struct mv88e6xxx_chip *chip = ds->priv;
1154 int stp_state;
1155 int err;
1156
1157 switch (state) {
1158 case BR_STATE_DISABLED:
1159 stp_state = PORT_CONTROL_STATE_DISABLED;
1160 break;
1161 case BR_STATE_BLOCKING:

--- 14 unchanged lines hidden (view full) ---

1176 mutex_unlock(&chip->reg_lock);
1177
1178 if (err)
1179 netdev_err(ds->ports[port].netdev,
1180 "failed to update state to %s\n",
1181 mv88e6xxx_port_state_names[stp_state]);
1182}
1183
1169 int stp_state;
1170 int err;
1171
1172 switch (state) {
1173 case BR_STATE_DISABLED:
1174 stp_state = PORT_CONTROL_STATE_DISABLED;
1175 break;
1176 case BR_STATE_BLOCKING:

--- 14 unchanged lines hidden (view full) ---

1191 mutex_unlock(&chip->reg_lock);
1192
1193 if (err)
1194 netdev_err(ds->ports[port].netdev,
1195 "failed to update state to %s\n",
1196 mv88e6xxx_port_state_names[stp_state]);
1197}
1198
1199static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1200{
1201 struct mv88e6xxx_chip *chip = ds->priv;
1202 int err;
1203
1204 mutex_lock(&chip->reg_lock);
1205 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1206 mutex_unlock(&chip->reg_lock);
1207
1208 if (err)
1209 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1210}
1211
1184static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1185 u16 *new, u16 *old)
1186{
1187 struct dsa_switch *ds = chip->ds;
1212static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1213 u16 *new, u16 *old)
1214{
1215 struct dsa_switch *ds = chip->ds;
1188 u16 pvid;
1189 int ret;
1216 u16 pvid, reg;
1217 int err;
1190
1218
1191 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1192 if (ret < 0)
1193 return ret;
1219 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, &reg);
1220 if (err)
1221 return err;
1194
1222
1195 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1223 pvid = reg & PORT_DEFAULT_VLAN_MASK;
1196
1197 if (new) {
1224
1225 if (new) {
1198 ret &= ~PORT_DEFAULT_VLAN_MASK;
1199 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1226 reg &= ~PORT_DEFAULT_VLAN_MASK;
1227 reg |= *new & PORT_DEFAULT_VLAN_MASK;
1200
1228
1201 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1202 PORT_DEFAULT_VLAN, ret);
1203 if (ret < 0)
1204 return ret;
1229 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
1230 if (err)
1231 return err;
1205
1206 netdev_dbg(ds->ports[port].netdev,
1207 "DefaultVID %d (was %d)\n", *new, pvid);
1208 }
1209
1210 if (old)
1211 *old = pvid;
1212

--- 9 unchanged lines hidden (view full) ---

1222static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1223 int port, u16 pvid)
1224{
1225 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1226}
1227
1228static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1229{
1232
1233 netdev_dbg(ds->ports[port].netdev,
1234 "DefaultVID %d (was %d)\n", *new, pvid);
1235 }
1236
1237 if (old)
1238 *old = pvid;
1239

--- 9 unchanged lines hidden (view full) ---

1249static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1250 int port, u16 pvid)
1251{
1252 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1253}
1254
1255static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1256{
1230 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1231 GLOBAL_VTU_OP_BUSY);
1257 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1232}
1233
1234static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1235{
1258}
1259
1260static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1261{
1236 int ret;
1262 int err;
1237
1263
1238 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1239 if (ret < 0)
1240 return ret;
1264 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1265 if (err)
1266 return err;
1241
1242 return _mv88e6xxx_vtu_wait(chip);
1243}
1244
1245static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1246{
1247 int ret;
1248

--- 4 unchanged lines hidden (view full) ---

1253 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1254}
1255
1256static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1257 struct mv88e6xxx_vtu_stu_entry *entry,
1258 unsigned int nibble_offset)
1259{
1260 u16 regs[3];
1267
1268 return _mv88e6xxx_vtu_wait(chip);
1269}
1270
1271static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1272{
1273 int ret;
1274

--- 4 unchanged lines hidden (view full) ---

1279 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1280}
1281
1282static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1283 struct mv88e6xxx_vtu_stu_entry *entry,
1284 unsigned int nibble_offset)
1285{
1286 u16 regs[3];
1261 int i;
1262 int ret;
1287 int i, err;
1263
1264 for (i = 0; i < 3; ++i) {
1288
1289 for (i = 0; i < 3; ++i) {
1265 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1266 GLOBAL_VTU_DATA_0_3 + i);
1267 if (ret < 0)
1268 return ret;
1290 u16 *reg = &regs[i];
1269
1291
1270 regs[i] = ret;
1292 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1293 if (err)
1294 return err;
1271 }
1272
1273 for (i = 0; i < chip->info->num_ports; ++i) {
1274 unsigned int shift = (i % 4) * 4 + nibble_offset;
1275 u16 reg = regs[i / 4];
1276
1277 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1278 }

--- 13 unchanged lines hidden (view full) ---

1292 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1293}
1294
1295static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1296 struct mv88e6xxx_vtu_stu_entry *entry,
1297 unsigned int nibble_offset)
1298{
1299 u16 regs[3] = { 0 };
1295 }
1296
1297 for (i = 0; i < chip->info->num_ports; ++i) {
1298 unsigned int shift = (i % 4) * 4 + nibble_offset;
1299 u16 reg = regs[i / 4];
1300
1301 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1302 }

--- 13 unchanged lines hidden (view full) ---

1316 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1317}
1318
1319static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1320 struct mv88e6xxx_vtu_stu_entry *entry,
1321 unsigned int nibble_offset)
1322{
1323 u16 regs[3] = { 0 };
1300 int i;
1301 int ret;
1324 int i, err;
1302
1303 for (i = 0; i < chip->info->num_ports; ++i) {
1304 unsigned int shift = (i % 4) * 4 + nibble_offset;
1305 u8 data = entry->data[i];
1306
1307 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1308 }
1309
1310 for (i = 0; i < 3; ++i) {
1325
1326 for (i = 0; i < chip->info->num_ports; ++i) {
1327 unsigned int shift = (i % 4) * 4 + nibble_offset;
1328 u8 data = entry->data[i];
1329
1330 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1331 }
1332
1333 for (i = 0; i < 3; ++i) {
1311 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1312 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1313 if (ret < 0)
1314 return ret;
1334 u16 reg = regs[i];
1335
1336 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1337 if (err)
1338 return err;
1315 }
1316
1317 return 0;
1318}
1319
1320static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1321 struct mv88e6xxx_vtu_stu_entry *entry)
1322{
1323 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1324}
1325
1326static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1327 struct mv88e6xxx_vtu_stu_entry *entry)
1328{
1329 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1330}
1331
1332static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1333{
1339 }
1340
1341 return 0;
1342}
1343
1344static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1345 struct mv88e6xxx_vtu_stu_entry *entry)
1346{
1347 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1348}
1349
1350static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1351 struct mv88e6xxx_vtu_stu_entry *entry)
1352{
1353 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1354}
1355
1356static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1357{
1334 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1335 vid & GLOBAL_VTU_VID_MASK);
1358 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1359 vid & GLOBAL_VTU_VID_MASK);
1336}
1337
1338static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1339 struct mv88e6xxx_vtu_stu_entry *entry)
1340{
1341 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1360}
1361
1362static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1363 struct mv88e6xxx_vtu_stu_entry *entry)
1364{
1365 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1342 int ret;
1366 u16 val;
1367 int err;
1343
1368
1344 ret = _mv88e6xxx_vtu_wait(chip);
1345 if (ret < 0)
1346 return ret;
1369 err = _mv88e6xxx_vtu_wait(chip);
1370 if (err)
1371 return err;
1347
1372
1348 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1349 if (ret < 0)
1350 return ret;
1373 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1374 if (err)
1375 return err;
1351
1376
1352 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1353 if (ret < 0)
1354 return ret;
1377 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1378 if (err)
1379 return err;
1355
1380
1356 next.vid = ret & GLOBAL_VTU_VID_MASK;
1357 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1381 next.vid = val & GLOBAL_VTU_VID_MASK;
1382 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1358
1359 if (next.valid) {
1383
1384 if (next.valid) {
1360 ret = mv88e6xxx_vtu_data_read(chip, &next);
1361 if (ret < 0)
1362 return ret;
1385 err = mv88e6xxx_vtu_data_read(chip, &next);
1386 if (err)
1387 return err;
1363
1364 if (mv88e6xxx_has_fid_reg(chip)) {
1388
1389 if (mv88e6xxx_has_fid_reg(chip)) {
1365 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1366 GLOBAL_VTU_FID);
1367 if (ret < 0)
1368 return ret;
1390 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1391 if (err)
1392 return err;
1369
1393
1370 next.fid = ret & GLOBAL_VTU_FID_MASK;
1394 next.fid = val & GLOBAL_VTU_FID_MASK;
1371 } else if (mv88e6xxx_num_databases(chip) == 256) {
1372 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1373 * VTU DBNum[3:0] are located in VTU Operation 3:0
1374 */
1395 } else if (mv88e6xxx_num_databases(chip) == 256) {
1396 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1397 * VTU DBNum[3:0] are located in VTU Operation 3:0
1398 */
1375 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1376 GLOBAL_VTU_OP);
1377 if (ret < 0)
1378 return ret;
1399 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1400 if (err)
1401 return err;
1379
1402
1380 next.fid = (ret & 0xf00) >> 4;
1381 next.fid |= ret & 0xf;
1403 next.fid = (val & 0xf00) >> 4;
1404 next.fid |= val & 0xf;
1382 }
1383
1384 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1405 }
1406
1407 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1385 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1386 GLOBAL_VTU_SID);
1387 if (ret < 0)
1388 return ret;
1408 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1409 if (err)
1410 return err;
1389
1411
1390 next.sid = ret & GLOBAL_VTU_SID_MASK;
1412 next.sid = val & GLOBAL_VTU_SID_MASK;
1391 }
1392 }
1393
1394 *entry = next;
1395 return 0;
1396}
1397
1398static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1399 struct switchdev_obj_port_vlan *vlan,
1400 int (*cb)(struct switchdev_obj *obj))
1401{
1413 }
1414 }
1415
1416 *entry = next;
1417 return 0;
1418}
1419
1420static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1421 struct switchdev_obj_port_vlan *vlan,
1422 int (*cb)(struct switchdev_obj *obj))
1423{
1402 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1424 struct mv88e6xxx_chip *chip = ds->priv;
1403 struct mv88e6xxx_vtu_stu_entry next;
1404 u16 pvid;
1405 int err;
1406
1407 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1408 return -EOPNOTSUPP;
1409
1410 mutex_lock(&chip->reg_lock);

--- 39 unchanged lines hidden (view full) ---

1450 return err;
1451}
1452
1453static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1454 struct mv88e6xxx_vtu_stu_entry *entry)
1455{
1456 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1457 u16 reg = 0;
1425 struct mv88e6xxx_vtu_stu_entry next;
1426 u16 pvid;
1427 int err;
1428
1429 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1430 return -EOPNOTSUPP;
1431
1432 mutex_lock(&chip->reg_lock);

--- 39 unchanged lines hidden (view full) ---

1472 return err;
1473}
1474
1475static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1476 struct mv88e6xxx_vtu_stu_entry *entry)
1477{
1478 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1479 u16 reg = 0;
1458 int ret;
1480 int err;
1459
1481
1460 ret = _mv88e6xxx_vtu_wait(chip);
1461 if (ret < 0)
1462 return ret;
1482 err = _mv88e6xxx_vtu_wait(chip);
1483 if (err)
1484 return err;
1463
1464 if (!entry->valid)
1465 goto loadpurge;
1466
1467 /* Write port member tags */
1485
1486 if (!entry->valid)
1487 goto loadpurge;
1488
1489 /* Write port member tags */
1468 ret = mv88e6xxx_vtu_data_write(chip, entry);
1469 if (ret < 0)
1470 return ret;
1490 err = mv88e6xxx_vtu_data_write(chip, entry);
1491 if (err)
1492 return err;
1471
1472 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1473 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1493
1494 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1495 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1474 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1475 reg);
1476 if (ret < 0)
1477 return ret;
1496 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1497 if (err)
1498 return err;
1478 }
1479
1480 if (mv88e6xxx_has_fid_reg(chip)) {
1481 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1499 }
1500
1501 if (mv88e6xxx_has_fid_reg(chip)) {
1502 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1482 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1483 reg);
1484 if (ret < 0)
1485 return ret;
1503 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1504 if (err)
1505 return err;
1486 } else if (mv88e6xxx_num_databases(chip) == 256) {
1487 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1488 * VTU DBNum[3:0] are located in VTU Operation 3:0
1489 */
1490 op |= (entry->fid & 0xf0) << 8;
1491 op |= entry->fid & 0xf;
1492 }
1493
1494 reg = GLOBAL_VTU_VID_VALID;
1495loadpurge:
1496 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1506 } else if (mv88e6xxx_num_databases(chip) == 256) {
1507 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1508 * VTU DBNum[3:0] are located in VTU Operation 3:0
1509 */
1510 op |= (entry->fid & 0xf0) << 8;
1511 op |= entry->fid & 0xf;
1512 }
1513
1514 reg = GLOBAL_VTU_VID_VALID;
1515loadpurge:
1516 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1497 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1498 if (ret < 0)
1499 return ret;
1517 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1518 if (err)
1519 return err;
1500
1501 return _mv88e6xxx_vtu_cmd(chip, op);
1502}
1503
1504static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1505 struct mv88e6xxx_vtu_stu_entry *entry)
1506{
1507 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1520
1521 return _mv88e6xxx_vtu_cmd(chip, op);
1522}
1523
1524static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1525 struct mv88e6xxx_vtu_stu_entry *entry)
1526{
1527 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1508 int ret;
1528 u16 val;
1529 int err;
1509
1530
1510 ret = _mv88e6xxx_vtu_wait(chip);
1511 if (ret < 0)
1512 return ret;
1531 err = _mv88e6xxx_vtu_wait(chip);
1532 if (err)
1533 return err;
1513
1534
1514 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1515 sid & GLOBAL_VTU_SID_MASK);
1516 if (ret < 0)
1517 return ret;
1535 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1536 sid & GLOBAL_VTU_SID_MASK);
1537 if (err)
1538 return err;
1518
1539
1519 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1520 if (ret < 0)
1521 return ret;
1540 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1541 if (err)
1542 return err;
1522
1543
1523 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1524 if (ret < 0)
1525 return ret;
1544 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1545 if (err)
1546 return err;
1526
1547
1527 next.sid = ret & GLOBAL_VTU_SID_MASK;
1548 next.sid = val & GLOBAL_VTU_SID_MASK;
1528
1549
1529 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1530 if (ret < 0)
1531 return ret;
1550 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1551 if (err)
1552 return err;
1532
1553
1533 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1554 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1534
1535 if (next.valid) {
1555
1556 if (next.valid) {
1536 ret = mv88e6xxx_stu_data_read(chip, &next);
1537 if (ret < 0)
1538 return ret;
1557 err = mv88e6xxx_stu_data_read(chip, &next);
1558 if (err)
1559 return err;
1539 }
1540
1541 *entry = next;
1542 return 0;
1543}
1544
1545static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1546 struct mv88e6xxx_vtu_stu_entry *entry)
1547{
1548 u16 reg = 0;
1560 }
1561
1562 *entry = next;
1563 return 0;
1564}
1565
1566static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1567 struct mv88e6xxx_vtu_stu_entry *entry)
1568{
1569 u16 reg = 0;
1549 int ret;
1570 int err;
1550
1571
1551 ret = _mv88e6xxx_vtu_wait(chip);
1552 if (ret < 0)
1553 return ret;
1572 err = _mv88e6xxx_vtu_wait(chip);
1573 if (err)
1574 return err;
1554
1555 if (!entry->valid)
1556 goto loadpurge;
1557
1558 /* Write port states */
1575
1576 if (!entry->valid)
1577 goto loadpurge;
1578
1579 /* Write port states */
1559 ret = mv88e6xxx_stu_data_write(chip, entry);
1560 if (ret < 0)
1561 return ret;
1580 err = mv88e6xxx_stu_data_write(chip, entry);
1581 if (err)
1582 return err;
1562
1563 reg = GLOBAL_VTU_VID_VALID;
1564loadpurge:
1583
1584 reg = GLOBAL_VTU_VID_VALID;
1585loadpurge:
1565 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1566 if (ret < 0)
1567 return ret;
1586 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1587 if (err)
1588 return err;
1568
1569 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1589
1590 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1570 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1571 if (ret < 0)
1572 return ret;
1591 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1592 if (err)
1593 return err;
1573
1574 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1575}
1576
1577static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1578 u16 *new, u16 *old)
1579{
1580 struct dsa_switch *ds = chip->ds;
1581 u16 upper_mask;
1582 u16 fid;
1594
1595 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1596}
1597
1598static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1599 u16 *new, u16 *old)
1600{
1601 struct dsa_switch *ds = chip->ds;
1602 u16 upper_mask;
1603 u16 fid;
1583 int ret;
1604 u16 reg;
1605 int err;
1584
1585 if (mv88e6xxx_num_databases(chip) == 4096)
1586 upper_mask = 0xff;
1587 else if (mv88e6xxx_num_databases(chip) == 256)
1588 upper_mask = 0xf;
1589 else
1590 return -EOPNOTSUPP;
1591
1592 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1606
1607 if (mv88e6xxx_num_databases(chip) == 4096)
1608 upper_mask = 0xff;
1609 else if (mv88e6xxx_num_databases(chip) == 256)
1610 upper_mask = 0xf;
1611 else
1612 return -EOPNOTSUPP;
1613
1614 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1593 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1594 if (ret < 0)
1595 return ret;
1615 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, &reg);
1616 if (err)
1617 return err;
1596
1618
1597 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1619 fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1598
1599 if (new) {
1620
1621 if (new) {
1600 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1601 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1622 reg &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1623 reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1602
1624
1603 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1604 ret);
1605 if (ret < 0)
1606 return ret;
1625 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1626 if (err)
1627 return err;
1607 }
1608
1609 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1628 }
1629
1630 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1610 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1611 if (ret < 0)
1612 return ret;
1631 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &reg);
1632 if (err)
1633 return err;
1613
1634
1614 fid |= (ret & upper_mask) << 4;
1635 fid |= (reg & upper_mask) << 4;
1615
1616 if (new) {
1636
1637 if (new) {
1617 ret &= ~upper_mask;
1618 ret |= (*new >> 4) & upper_mask;
1638 reg &= ~upper_mask;
1639 reg |= (*new >> 4) & upper_mask;
1619
1640
1620 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1621 ret);
1622 if (ret < 0)
1623 return ret;
1641 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
1642 if (err)
1643 return err;
1624
1625 netdev_dbg(ds->ports[port].netdev,
1626 "FID %d (was %d)\n", *new, fid);
1627 }
1628
1629 if (old)
1630 *old = fid;
1631

--- 131 unchanged lines hidden (view full) ---

1763 }
1764
1765 return err;
1766}
1767
1768static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1769 u16 vid_begin, u16 vid_end)
1770{
1644
1645 netdev_dbg(ds->ports[port].netdev,
1646 "FID %d (was %d)\n", *new, fid);
1647 }
1648
1649 if (old)
1650 *old = fid;
1651

--- 131 unchanged lines hidden (view full) ---

1783 }
1784
1785 return err;
1786}
1787
1788static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1789 u16 vid_begin, u16 vid_end)
1790{
1771 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1791 struct mv88e6xxx_chip *chip = ds->priv;
1772 struct mv88e6xxx_vtu_stu_entry vlan;
1773 int i, err;
1774
1775 if (!vid_begin)
1776 return -EOPNOTSUPP;
1777
1778 mutex_lock(&chip->reg_lock);
1779

--- 44 unchanged lines hidden (view full) ---

1824 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1825 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1826 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1827};
1828
1829static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1830 bool vlan_filtering)
1831{
1792 struct mv88e6xxx_vtu_stu_entry vlan;
1793 int i, err;
1794
1795 if (!vid_begin)
1796 return -EOPNOTSUPP;
1797
1798 mutex_lock(&chip->reg_lock);
1799

--- 44 unchanged lines hidden (view full) ---

1844 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1845 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1846 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1847};
1848
1849static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1850 bool vlan_filtering)
1851{
1832 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1852 struct mv88e6xxx_chip *chip = ds->priv;
1833 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1834 PORT_CONTROL_2_8021Q_DISABLED;
1853 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1854 PORT_CONTROL_2_8021Q_DISABLED;
1835 int ret;
1855 u16 reg;
1856 int err;
1836
1837 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1838 return -EOPNOTSUPP;
1839
1840 mutex_lock(&chip->reg_lock);
1841
1857
1858 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1859 return -EOPNOTSUPP;
1860
1861 mutex_lock(&chip->reg_lock);
1862
1842 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1843 if (ret < 0)
1863 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, &reg);
1864 if (err)
1844 goto unlock;
1845
1865 goto unlock;
1866
1846 old = ret & PORT_CONTROL_2_8021Q_MASK;
1867 old = reg & PORT_CONTROL_2_8021Q_MASK;
1847
1848 if (new != old) {
1868
1869 if (new != old) {
1849 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1850 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1870 reg &= ~PORT_CONTROL_2_8021Q_MASK;
1871 reg |= new & PORT_CONTROL_2_8021Q_MASK;
1851
1872
1852 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1853 ret);
1854 if (ret < 0)
1873 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
1874 if (err)
1855 goto unlock;
1856
1857 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1858 mv88e6xxx_port_8021q_mode_names[new],
1859 mv88e6xxx_port_8021q_mode_names[old]);
1860 }
1861
1875 goto unlock;
1876
1877 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1878 mv88e6xxx_port_8021q_mode_names[new],
1879 mv88e6xxx_port_8021q_mode_names[old]);
1880 }
1881
1862 ret = 0;
1882 err = 0;
1863unlock:
1864 mutex_unlock(&chip->reg_lock);
1865
1883unlock:
1884 mutex_unlock(&chip->reg_lock);
1885
1866 return ret;
1886 return err;
1867}
1868
1869static int
1870mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1871 const struct switchdev_obj_port_vlan *vlan,
1872 struct switchdev_trans *trans)
1873{
1887}
1888
1889static int
1890mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1891 const struct switchdev_obj_port_vlan *vlan,
1892 struct switchdev_trans *trans)
1893{
1874 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1894 struct mv88e6xxx_chip *chip = ds->priv;
1875 int err;
1876
1877 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1878 return -EOPNOTSUPP;
1879
1880 /* If the requested port doesn't belong to the same bridge as the VLAN
1881 * members, do not support it (yet) and fallback to software VLAN.
1882 */

--- 24 unchanged lines hidden (view full) ---

1907
1908 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1909}
1910
1911static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1912 const struct switchdev_obj_port_vlan *vlan,
1913 struct switchdev_trans *trans)
1914{
1895 int err;
1896
1897 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1898 return -EOPNOTSUPP;
1899
1900 /* If the requested port doesn't belong to the same bridge as the VLAN
1901 * members, do not support it (yet) and fallback to software VLAN.
1902 */

--- 24 unchanged lines hidden (view full) ---

1927
1928 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1929}
1930
1931static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1932 const struct switchdev_obj_port_vlan *vlan,
1933 struct switchdev_trans *trans)
1934{
1915 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1935 struct mv88e6xxx_chip *chip = ds->priv;
1916 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1917 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1918 u16 vid;
1919
1920 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1921 return;
1922
1923 mutex_lock(&chip->reg_lock);

--- 45 unchanged lines hidden (view full) ---

1969 return err;
1970
1971 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1972}
1973
1974static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1975 const struct switchdev_obj_port_vlan *vlan)
1976{
1936 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1937 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1938 u16 vid;
1939
1940 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1941 return;
1942
1943 mutex_lock(&chip->reg_lock);

--- 45 unchanged lines hidden (view full) ---

1989 return err;
1990
1991 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1992}
1993
1994static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1995 const struct switchdev_obj_port_vlan *vlan)
1996{
1977 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1997 struct mv88e6xxx_chip *chip = ds->priv;
1978 u16 pvid, vid;
1979 int err = 0;
1980
1981 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1982 return -EOPNOTSUPP;
1983
1984 mutex_lock(&chip->reg_lock);
1985

--- 17 unchanged lines hidden (view full) ---

2003 mutex_unlock(&chip->reg_lock);
2004
2005 return err;
2006}
2007
2008static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2009 const unsigned char *addr)
2010{
1998 u16 pvid, vid;
1999 int err = 0;
2000
2001 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2002 return -EOPNOTSUPP;
2003
2004 mutex_lock(&chip->reg_lock);
2005

--- 17 unchanged lines hidden (view full) ---

2023 mutex_unlock(&chip->reg_lock);
2024
2025 return err;
2026}
2027
2028static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2029 const unsigned char *addr)
2030{
2011 int i, ret;
2031 int i, err;
2012
2013 for (i = 0; i < 3; i++) {
2032
2033 for (i = 0; i < 3; i++) {
2014 ret = _mv88e6xxx_reg_write(
2015 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2016 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2017 if (ret < 0)
2018 return ret;
2034 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
2035 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2036 if (err)
2037 return err;
2019 }
2020
2021 return 0;
2022}
2023
2024static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2025 unsigned char *addr)
2026{
2038 }
2039
2040 return 0;
2041}
2042
2043static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2044 unsigned char *addr)
2045{
2027 int i, ret;
2046 u16 val;
2047 int i, err;
2028
2029 for (i = 0; i < 3; i++) {
2048
2049 for (i = 0; i < 3; i++) {
2030 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2031 GLOBAL_ATU_MAC_01 + i);
2032 if (ret < 0)
2033 return ret;
2034 addr[i * 2] = ret >> 8;
2035 addr[i * 2 + 1] = ret & 0xff;
2050 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
2051 if (err)
2052 return err;
2053
2054 addr[i * 2] = val >> 8;
2055 addr[i * 2 + 1] = val & 0xff;
2036 }
2037
2038 return 0;
2039}
2040
2041static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2042 struct mv88e6xxx_atu_entry *entry)
2043{

--- 9 unchanged lines hidden (view full) ---

2053
2054 ret = _mv88e6xxx_atu_data_write(chip, entry);
2055 if (ret < 0)
2056 return ret;
2057
2058 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2059}
2060
2056 }
2057
2058 return 0;
2059}
2060
2061static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2062 struct mv88e6xxx_atu_entry *entry)
2063{

--- 9 unchanged lines hidden (view full) ---

2073
2074 ret = _mv88e6xxx_atu_data_write(chip, entry);
2075 if (ret < 0)
2076 return ret;
2077
2078 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2079}
2080
2061static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2062 const unsigned char *addr, u16 vid,
2063 u8 state)
2081static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2082 struct mv88e6xxx_atu_entry *entry);
2083
2084static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2085 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2064{
2086{
2065 struct mv88e6xxx_atu_entry entry = { 0 };
2087 struct mv88e6xxx_atu_entry next;
2088 int err;
2089
2090 eth_broadcast_addr(next.mac);
2091
2092 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2093 if (err)
2094 return err;
2095
2096 do {
2097 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2098 if (err)
2099 return err;
2100
2101 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2102 break;
2103
2104 if (ether_addr_equal(next.mac, addr)) {
2105 *entry = next;
2106 return 0;
2107 }
2108 } while (!is_broadcast_ether_addr(next.mac));
2109
2110 memset(entry, 0, sizeof(*entry));
2111 entry->fid = fid;
2112 ether_addr_copy(entry->mac, addr);
2113
2114 return 0;
2115}
2116
2117static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2118 const unsigned char *addr, u16 vid,
2119 u8 state)
2120{
2066 struct mv88e6xxx_vtu_stu_entry vlan;
2121 struct mv88e6xxx_vtu_stu_entry vlan;
2122 struct mv88e6xxx_atu_entry entry;
2067 int err;
2068
2069 /* Null VLAN ID corresponds to the port private database */
2070 if (vid == 0)
2071 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2072 else
2073 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2074 if (err)
2075 return err;
2076
2123 int err;
2124
2125 /* Null VLAN ID corresponds to the port private database */
2126 if (vid == 0)
2127 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2128 else
2129 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2130 if (err)
2131 return err;
2132
2077 entry.fid = vlan.fid;
2078 entry.state = state;
2079 ether_addr_copy(entry.mac, addr);
2080 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2081 entry.trunk = false;
2082 entry.portv_trunkid = BIT(port);
2133 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2134 if (err)
2135 return err;
2136
2137 /* Purge the ATU entry only if no port is using it anymore */
2138 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2139 entry.portv_trunkid &= ~BIT(port);
2140 if (!entry.portv_trunkid)
2141 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2142 } else {
2143 entry.portv_trunkid |= BIT(port);
2144 entry.state = state;
2083 }
2084
2085 return _mv88e6xxx_atu_load(chip, &entry);
2086}
2087
2088static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2089 const struct switchdev_obj_port_fdb *fdb,
2090 struct switchdev_trans *trans)
2091{
2092 /* We don't need any dynamic resource from the kernel (yet),
2093 * so skip the prepare phase.
2094 */
2095 return 0;
2096}
2097
2098static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2099 const struct switchdev_obj_port_fdb *fdb,
2100 struct switchdev_trans *trans)
2101{
2145 }
2146
2147 return _mv88e6xxx_atu_load(chip, &entry);
2148}
2149
2150static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2151 const struct switchdev_obj_port_fdb *fdb,
2152 struct switchdev_trans *trans)
2153{
2154 /* We don't need any dynamic resource from the kernel (yet),
2155 * so skip the prepare phase.
2156 */
2157 return 0;
2158}
2159
2160static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2161 const struct switchdev_obj_port_fdb *fdb,
2162 struct switchdev_trans *trans)
2163{
2102 int state = is_multicast_ether_addr(fdb->addr) ?
2103 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2104 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2105 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2164 struct mv88e6xxx_chip *chip = ds->priv;
2106
2107 mutex_lock(&chip->reg_lock);
2165
2166 mutex_lock(&chip->reg_lock);
2108 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2109 netdev_err(ds->ports[port].netdev,
2110 "failed to load MAC address\n");
2167 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2168 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2169 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2111 mutex_unlock(&chip->reg_lock);
2112}
2113
2114static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2115 const struct switchdev_obj_port_fdb *fdb)
2116{
2170 mutex_unlock(&chip->reg_lock);
2171}
2172
2173static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2174 const struct switchdev_obj_port_fdb *fdb)
2175{
2117 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2118 int ret;
2176 struct mv88e6xxx_chip *chip = ds->priv;
2177 int err;
2119
2120 mutex_lock(&chip->reg_lock);
2178
2179 mutex_lock(&chip->reg_lock);
2121 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2122 GLOBAL_ATU_DATA_STATE_UNUSED);
2180 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2181 GLOBAL_ATU_DATA_STATE_UNUSED);
2123 mutex_unlock(&chip->reg_lock);
2124
2182 mutex_unlock(&chip->reg_lock);
2183
2125 return ret;
2184 return err;
2126}
2127
2128static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2129 struct mv88e6xxx_atu_entry *entry)
2130{
2131 struct mv88e6xxx_atu_entry next = { 0 };
2185}
2186
2187static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2188 struct mv88e6xxx_atu_entry *entry)
2189{
2190 struct mv88e6xxx_atu_entry next = { 0 };
2132 int ret;
2191 u16 val;
2192 int err;
2133
2134 next.fid = fid;
2135
2193
2194 next.fid = fid;
2195
2136 ret = _mv88e6xxx_atu_wait(chip);
2137 if (ret < 0)
2138 return ret;
2196 err = _mv88e6xxx_atu_wait(chip);
2197 if (err)
2198 return err;
2139
2199
2140 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2141 if (ret < 0)
2142 return ret;
2200 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2201 if (err)
2202 return err;
2143
2203
2144 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2145 if (ret < 0)
2146 return ret;
2204 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2205 if (err)
2206 return err;
2147
2207
2148 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2149 if (ret < 0)
2150 return ret;
2208 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2209 if (err)
2210 return err;
2151
2211
2152 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2212 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2153 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2154 unsigned int mask, shift;
2155
2213 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2214 unsigned int mask, shift;
2215
2156 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2216 if (val & GLOBAL_ATU_DATA_TRUNK) {
2157 next.trunk = true;
2158 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2159 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2160 } else {
2161 next.trunk = false;
2162 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2163 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2164 }
2165
2217 next.trunk = true;
2218 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2219 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2220 } else {
2221 next.trunk = false;
2222 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2223 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2224 }
2225
2166 next.portv_trunkid = (ret & mask) >> shift;
2226 next.portv_trunkid = (val & mask) >> shift;
2167 }
2168
2169 *entry = next;
2170 return 0;
2171}
2172
2227 }
2228
2229 *entry = next;
2230 return 0;
2231}
2232
2173static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2174 u16 fid, u16 vid, int port,
2175 struct switchdev_obj_port_fdb *fdb,
2176 int (*cb)(struct switchdev_obj *obj))
2233static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2234 u16 fid, u16 vid, int port,
2235 struct switchdev_obj *obj,
2236 int (*cb)(struct switchdev_obj *obj))
2177{
2178 struct mv88e6xxx_atu_entry addr = {
2179 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2180 };
2181 int err;
2182
2183 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2184 if (err)
2185 return err;
2186
2187 do {
2188 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2189 if (err)
2237{
2238 struct mv88e6xxx_atu_entry addr = {
2239 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2240 };
2241 int err;
2242
2243 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2244 if (err)
2245 return err;
2246
2247 do {
2248 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2249 if (err)
2190 break;
2250 return err;
2191
2192 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2193 break;
2194
2251
2252 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2253 break;
2254
2195 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2196 bool is_static = addr.state ==
2197 (is_multicast_ether_addr(addr.mac) ?
2198 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2199 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2255 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2256 continue;
2200
2257
2258 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2259 struct switchdev_obj_port_fdb *fdb;
2260
2261 if (!is_unicast_ether_addr(addr.mac))
2262 continue;
2263
2264 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2201 fdb->vid = vid;
2202 ether_addr_copy(fdb->addr, addr.mac);
2265 fdb->vid = vid;
2266 ether_addr_copy(fdb->addr, addr.mac);
2203 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2267 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2268 fdb->ndm_state = NUD_NOARP;
2269 else
2270 fdb->ndm_state = NUD_REACHABLE;
2271 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2272 struct switchdev_obj_port_mdb *mdb;
2204
2273
2205 err = cb(&fdb->obj);
2206 if (err)
2207 break;
2274 if (!is_multicast_ether_addr(addr.mac))
2275 continue;
2276
2277 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2278 mdb->vid = vid;
2279 ether_addr_copy(mdb->addr, addr.mac);
2280 } else {
2281 return -EOPNOTSUPP;
2208 }
2282 }
2283
2284 err = cb(obj);
2285 if (err)
2286 return err;
2209 } while (!is_broadcast_ether_addr(addr.mac));
2210
2211 return err;
2212}
2213
2287 } while (!is_broadcast_ether_addr(addr.mac));
2288
2289 return err;
2290}
2291
2214static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2215 struct switchdev_obj_port_fdb *fdb,
2216 int (*cb)(struct switchdev_obj *obj))
2292static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2293 struct switchdev_obj *obj,
2294 int (*cb)(struct switchdev_obj *obj))
2217{
2295{
2218 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2219 struct mv88e6xxx_vtu_stu_entry vlan = {
2220 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2221 };
2222 u16 fid;
2223 int err;
2224
2296 struct mv88e6xxx_vtu_stu_entry vlan = {
2297 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2298 };
2299 u16 fid;
2300 int err;
2301
2225 mutex_lock(&chip->reg_lock);
2226
2227 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2228 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2229 if (err)
2302 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2303 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2304 if (err)
2230 goto unlock;
2305 return err;
2231
2306
2232 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2307 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2233 if (err)
2308 if (err)
2234 goto unlock;
2309 return err;
2235
2236 /* Dump VLANs' Filtering Information Databases */
2237 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2238 if (err)
2310
2311 /* Dump VLANs' Filtering Information Databases */
2312 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2313 if (err)
2239 goto unlock;
2314 return err;
2240
2241 do {
2242 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2243 if (err)
2315
2316 do {
2317 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2318 if (err)
2244 break;
2319 return err;
2245
2246 if (!vlan.valid)
2247 break;
2248
2320
2321 if (!vlan.valid)
2322 break;
2323
2249 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2250 port, fdb, cb);
2324 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2325 obj, cb);
2251 if (err)
2326 if (err)
2252 break;
2327 return err;
2253 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2254
2328 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2329
2255unlock:
2330 return err;
2331}
2332
2333static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2334 struct switchdev_obj_port_fdb *fdb,
2335 int (*cb)(struct switchdev_obj *obj))
2336{
2337 struct mv88e6xxx_chip *chip = ds->priv;
2338 int err;
2339
2340 mutex_lock(&chip->reg_lock);
2341 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2256 mutex_unlock(&chip->reg_lock);
2257
2258 return err;
2259}
2260
2261static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2262 struct net_device *bridge)
2263{
2342 mutex_unlock(&chip->reg_lock);
2343
2344 return err;
2345}
2346
2347static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2348 struct net_device *bridge)
2349{
2264 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2350 struct mv88e6xxx_chip *chip = ds->priv;
2265 int i, err = 0;
2266
2267 mutex_lock(&chip->reg_lock);
2268
2269 /* Assign the bridge and remap each port's VLANTable */
2270 chip->ports[port].bridge_dev = bridge;
2271
2272 for (i = 0; i < chip->info->num_ports; ++i) {

--- 6 unchanged lines hidden (view full) ---

2279
2280 mutex_unlock(&chip->reg_lock);
2281
2282 return err;
2283}
2284
2285static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2286{
2351 int i, err = 0;
2352
2353 mutex_lock(&chip->reg_lock);
2354
2355 /* Assign the bridge and remap each port's VLANTable */
2356 chip->ports[port].bridge_dev = bridge;
2357
2358 for (i = 0; i < chip->info->num_ports; ++i) {

--- 6 unchanged lines hidden (view full) ---

2365
2366 mutex_unlock(&chip->reg_lock);
2367
2368 return err;
2369}
2370
2371static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2372{
2287 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2373 struct mv88e6xxx_chip *chip = ds->priv;
2288 struct net_device *bridge = chip->ports[port].bridge_dev;
2289 int i;
2290
2291 mutex_lock(&chip->reg_lock);
2292
2293 /* Unassign the bridge and remap each port's VLANTable */
2294 chip->ports[port].bridge_dev = NULL;
2295
2296 for (i = 0; i < chip->info->num_ports; ++i)
2297 if (i == port || chip->ports[i].bridge_dev == bridge)
2298 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2299 netdev_warn(ds->ports[i].netdev,
2300 "failed to remap\n");
2301
2302 mutex_unlock(&chip->reg_lock);
2303}
2304
2374 struct net_device *bridge = chip->ports[port].bridge_dev;
2375 int i;
2376
2377 mutex_lock(&chip->reg_lock);
2378
2379 /* Unassign the bridge and remap each port's VLANTable */
2380 chip->ports[port].bridge_dev = NULL;
2381
2382 for (i = 0; i < chip->info->num_ports; ++i)
2383 if (i == port || chip->ports[i].bridge_dev == bridge)
2384 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2385 netdev_warn(ds->ports[i].netdev,
2386 "failed to remap\n");
2387
2388 mutex_unlock(&chip->reg_lock);
2389}
2390
2305static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2306 int port, int page, int reg, int val)
2307{
2308 int ret;
2309
2310 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2311 if (ret < 0)
2312 goto restore_page_0;
2313
2314 ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2315restore_page_0:
2316 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2317
2318 return ret;
2319}
2320
2321static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2322 int port, int page, int reg)
2323{
2324 int ret;
2325
2326 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2327 if (ret < 0)
2328 goto restore_page_0;
2329
2330 ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2331restore_page_0:
2332 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2333
2334 return ret;
2335}
2336
2337static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2338{
2339 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2340 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2341 struct gpio_desc *gpiod = chip->reset;
2342 unsigned long timeout;
2391static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2392{
2393 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2394 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2395 struct gpio_desc *gpiod = chip->reset;
2396 unsigned long timeout;
2343 int ret;
2397 u16 reg;
2398 int err;
2344 int i;
2345
2346 /* Set all ports to the disabled state. */
2347 for (i = 0; i < chip->info->num_ports; i++) {
2399 int i;
2400
2401 /* Set all ports to the disabled state. */
2402 for (i = 0; i < chip->info->num_ports; i++) {
2348 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2349 if (ret < 0)
2350 return ret;
2403 err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, &reg);
2404 if (err)
2405 return err;
2351
2406
2352 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2353 ret & 0xfffc);
2354 if (ret)
2355 return ret;
2407 err = mv88e6xxx_port_write(chip, i, PORT_CONTROL,
2408 reg & 0xfffc);
2409 if (err)
2410 return err;
2356 }
2357
2358 /* Wait for transmit queues to drain. */
2359 usleep_range(2000, 4000);
2360
2361 /* If there is a gpio connected to the reset pin, toggle it */
2362 if (gpiod) {
2363 gpiod_set_value_cansleep(gpiod, 1);
2364 usleep_range(10000, 20000);
2365 gpiod_set_value_cansleep(gpiod, 0);
2366 usleep_range(10000, 20000);
2367 }
2368
2369 /* Reset the switch. Keep the PPU active if requested. The PPU
2370 * needs to be active to support indirect phy register access
2371 * through global registers 0x18 and 0x19.
2372 */
2373 if (ppu_active)
2411 }
2412
2413 /* Wait for transmit queues to drain. */
2414 usleep_range(2000, 4000);
2415
2416 /* If there is a gpio connected to the reset pin, toggle it */
2417 if (gpiod) {
2418 gpiod_set_value_cansleep(gpiod, 1);
2419 usleep_range(10000, 20000);
2420 gpiod_set_value_cansleep(gpiod, 0);
2421 usleep_range(10000, 20000);
2422 }
2423
2424 /* Reset the switch. Keep the PPU active if requested. The PPU
2425 * needs to be active to support indirect phy register access
2426 * through global registers 0x18 and 0x19.
2427 */
2428 if (ppu_active)
2374 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2429 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000);
2375 else
2430 else
2376 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2377 if (ret)
2378 return ret;
2431 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400);
2432 if (err)
2433 return err;
2379
2380 /* Wait up to one second for reset to complete. */
2381 timeout = jiffies + 1 * HZ;
2382 while (time_before(jiffies, timeout)) {
2434
2435 /* Wait up to one second for reset to complete. */
2436 timeout = jiffies + 1 * HZ;
2437 while (time_before(jiffies, timeout)) {
2383 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2384 if (ret < 0)
2385 return ret;
2438 err = mv88e6xxx_g1_read(chip, 0x00, &reg);
2439 if (err)
2440 return err;
2386
2441
2387 if ((ret & is_reset) == is_reset)
2442 if ((reg & is_reset) == is_reset)
2388 break;
2389 usleep_range(1000, 2000);
2390 }
2391 if (time_after(jiffies, timeout))
2443 break;
2444 usleep_range(1000, 2000);
2445 }
2446 if (time_after(jiffies, timeout))
2392 ret = -ETIMEDOUT;
2447 err = -ETIMEDOUT;
2393 else
2448 else
2394 ret = 0;
2449 err = 0;
2395
2450
2396 return ret;
2451 return err;
2397}
2398
2452}
2453
2399static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2454static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2400{
2455{
2401 int ret;
2456 u16 val;
2457 int err;
2402
2458
2403 ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2404 PAGE_FIBER_SERDES, MII_BMCR);
2405 if (ret < 0)
2406 return ret;
2459 /* Clear Power Down bit */
2460 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2461 if (err)
2462 return err;
2407
2463
2408 if (ret & BMCR_PDOWN) {
2409 ret &= ~BMCR_PDOWN;
2410 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2411 PAGE_FIBER_SERDES, MII_BMCR,
2412 ret);
2464 if (val & BMCR_PDOWN) {
2465 val &= ~BMCR_PDOWN;
2466 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2413 }
2414
2467 }
2468
2415 return ret;
2469 return err;
2416}
2417
2470}
2471
2418static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2419 int reg, u16 *val)
2420{
2421 int addr = chip->info->port_base_addr + port;
2422
2423 if (port >= chip->info->num_ports)
2424 return -EINVAL;
2425
2426 return mv88e6xxx_read(chip, addr, reg, val);
2427}
2428
2429static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2430{
2431 struct dsa_switch *ds = chip->ds;
2472static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2473{
2474 struct dsa_switch *ds = chip->ds;
2432 int ret;
2475 int err;
2433 u16 reg;
2434
2435 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2436 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2437 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2438 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2439 /* MAC Forcing register: don't force link, speed,
2440 * duplex or flow control state to any particular
2441 * values on physical ports, but force the CPU port
2442 * and all DSA ports to their maximum bandwidth and
2443 * full duplex.
2444 */
2476 u16 reg;
2477
2478 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2479 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2480 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2481 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2482 /* MAC Forcing register: don't force link, speed,
2483 * duplex or flow control state to any particular
2484 * values on physical ports, but force the CPU port
2485 * and all DSA ports to their maximum bandwidth and
2486 * full duplex.
2487 */
2445 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2488 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, &reg);
2446 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2447 reg &= ~PORT_PCS_CTRL_UNFORCED;
2448 reg |= PORT_PCS_CTRL_FORCE_LINK |
2449 PORT_PCS_CTRL_LINK_UP |
2450 PORT_PCS_CTRL_DUPLEX_FULL |
2451 PORT_PCS_CTRL_FORCE_DUPLEX;
2452 if (mv88e6xxx_6065_family(chip))
2453 reg |= PORT_PCS_CTRL_100;
2454 else
2455 reg |= PORT_PCS_CTRL_1000;
2456 } else {
2457 reg |= PORT_PCS_CTRL_UNFORCED;
2458 }
2459
2489 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2490 reg &= ~PORT_PCS_CTRL_UNFORCED;
2491 reg |= PORT_PCS_CTRL_FORCE_LINK |
2492 PORT_PCS_CTRL_LINK_UP |
2493 PORT_PCS_CTRL_DUPLEX_FULL |
2494 PORT_PCS_CTRL_FORCE_DUPLEX;
2495 if (mv88e6xxx_6065_family(chip))
2496 reg |= PORT_PCS_CTRL_100;
2497 else
2498 reg |= PORT_PCS_CTRL_1000;
2499 } else {
2500 reg |= PORT_PCS_CTRL_UNFORCED;
2501 }
2502
2460 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2461 PORT_PCS_CTRL, reg);
2462 if (ret)
2463 return ret;
2503 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
2504 if (err)
2505 return err;
2464 }
2465
2466 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2467 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2468 * tunneling, determine priority by looking at 802.1p and IP
2469 * priority fields (IP prio has precedence), and set STP state
2470 * to Forwarding.
2471 *

--- 9 unchanged lines hidden (view full) ---

2481 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2482 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2483 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2484 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2485 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2486 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2487 PORT_CONTROL_STATE_FORWARDING;
2488 if (dsa_is_cpu_port(ds, port)) {
2506 }
2507
2508 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2509 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2510 * tunneling, determine priority by looking at 802.1p and IP
2511 * priority fields (IP prio has precedence), and set STP state
2512 * to Forwarding.
2513 *

--- 9 unchanged lines hidden (view full) ---

2523 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2524 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2525 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2526 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2527 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2528 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2529 PORT_CONTROL_STATE_FORWARDING;
2530 if (dsa_is_cpu_port(ds, port)) {
2489 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2490 reg |= PORT_CONTROL_DSA_TAG;
2491 if (mv88e6xxx_6352_family(chip) ||
2492 mv88e6xxx_6351_family(chip) ||
2493 mv88e6xxx_6165_family(chip) ||
2494 mv88e6xxx_6097_family(chip) ||
2495 mv88e6xxx_6320_family(chip)) {
2531 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2496 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2532 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2497 PORT_CONTROL_FORWARD_UNKNOWN |
2498 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2533 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2499 }
2500
2501 if (mv88e6xxx_6352_family(chip) ||
2502 mv88e6xxx_6351_family(chip) ||
2503 mv88e6xxx_6165_family(chip) ||
2504 mv88e6xxx_6097_family(chip) ||
2505 mv88e6xxx_6095_family(chip) ||
2506 mv88e6xxx_6065_family(chip) ||
2507 mv88e6xxx_6185_family(chip) ||
2508 mv88e6xxx_6320_family(chip)) {
2509 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2510 }
2534 else
2535 reg |= PORT_CONTROL_DSA_TAG;
2536 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2537 PORT_CONTROL_FORWARD_UNKNOWN;
2511 }
2512 if (dsa_is_dsa_port(ds, port)) {
2513 if (mv88e6xxx_6095_family(chip) ||
2514 mv88e6xxx_6185_family(chip))
2515 reg |= PORT_CONTROL_DSA_TAG;
2516 if (mv88e6xxx_6352_family(chip) ||
2517 mv88e6xxx_6351_family(chip) ||
2518 mv88e6xxx_6165_family(chip) ||
2519 mv88e6xxx_6097_family(chip) ||
2520 mv88e6xxx_6320_family(chip)) {
2521 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2522 }
2523
2524 if (port == dsa_upstream_port(ds))
2525 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2526 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2527 }
2528 if (reg) {
2538 }
2539 if (dsa_is_dsa_port(ds, port)) {
2540 if (mv88e6xxx_6095_family(chip) ||
2541 mv88e6xxx_6185_family(chip))
2542 reg |= PORT_CONTROL_DSA_TAG;
2543 if (mv88e6xxx_6352_family(chip) ||
2544 mv88e6xxx_6351_family(chip) ||
2545 mv88e6xxx_6165_family(chip) ||
2546 mv88e6xxx_6097_family(chip) ||
2547 mv88e6xxx_6320_family(chip)) {
2548 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2549 }
2550
2551 if (port == dsa_upstream_port(ds))
2552 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2553 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2554 }
2555 if (reg) {
2529 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2530 PORT_CONTROL, reg);
2531 if (ret)
2532 return ret;
2556 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2557 if (err)
2558 return err;
2533 }
2534
2535 /* If this port is connected to a SerDes, make sure the SerDes is not
2536 * powered down.
2537 */
2559 }
2560
2561 /* If this port is connected to a SerDes, make sure the SerDes is not
2562 * powered down.
2563 */
2538 if (mv88e6xxx_6352_family(chip)) {
2539 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2540 if (ret < 0)
2541 return ret;
2542 ret &= PORT_STATUS_CMODE_MASK;
2543 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2544 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2545 (ret == PORT_STATUS_CMODE_SGMII)) {
2546 ret = mv88e6xxx_power_on_serdes(chip);
2547 if (ret < 0)
2548 return ret;
2564 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2565 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2566 if (err)
2567 return err;
2568 reg &= PORT_STATUS_CMODE_MASK;
2569 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2570 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2571 (reg == PORT_STATUS_CMODE_SGMII)) {
2572 err = mv88e6xxx_serdes_power_on(chip);
2573 if (err < 0)
2574 return err;
2549 }
2550 }
2551
2552 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2553 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2554 * untagged frames on this port, do a destination address lookup on all
2555 * received packets as usual, disable ARP mirroring and don't send a
2556 * copy of all transmitted/received frames on this port to the CPU.

--- 17 unchanged lines hidden (view full) ---

2574 */
2575 if (port == dsa_upstream_port(ds))
2576 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2577 }
2578
2579 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2580
2581 if (reg) {
2575 }
2576 }
2577
2578 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2579 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2580 * untagged frames on this port, do a destination address lookup on all
2581 * received packets as usual, disable ARP mirroring and don't send a
2582 * copy of all transmitted/received frames on this port to the CPU.

--- 17 unchanged lines hidden (view full) ---

2600 */
2601 if (port == dsa_upstream_port(ds))
2602 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2603 }
2604
2605 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2606
2607 if (reg) {
2582 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2583 PORT_CONTROL_2, reg);
2584 if (ret)
2585 return ret;
2608 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2609 if (err)
2610 return err;
2586 }
2587
2588 /* Port Association Vector: when learning source addresses
2589 * of packets, add the address to the address database using
2590 * a port bitmap that has only the bit for this port set and
2591 * the other bits clear.
2592 */
2593 reg = 1 << port;
2594 /* Disable learning for CPU port */
2595 if (dsa_is_cpu_port(ds, port))
2596 reg = 0;
2597
2611 }
2612
2613 /* Port Association Vector: when learning source addresses
2614 * of packets, add the address to the address database using
2615 * a port bitmap that has only the bit for this port set and
2616 * the other bits clear.
2617 */
2618 reg = 1 << port;
2619 /* Disable learning for CPU port */
2620 if (dsa_is_cpu_port(ds, port))
2621 reg = 0;
2622
2598 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2599 reg);
2600 if (ret)
2601 return ret;
2623 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2624 if (err)
2625 return err;
2602
2603 /* Egress rate control 2: disable egress rate control. */
2626
2627 /* Egress rate control 2: disable egress rate control. */
2604 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2605 0x0000);
2606 if (ret)
2607 return ret;
2628 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2629 if (err)
2630 return err;
2608
2609 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2610 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2611 mv88e6xxx_6320_family(chip)) {
2612 /* Do not limit the period of time that this port can
2613 * be paused for by the remote end or the period of
2614 * time that this port can pause the remote end.
2615 */
2631
2632 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2633 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2634 mv88e6xxx_6320_family(chip)) {
2635 /* Do not limit the period of time that this port can
2636 * be paused for by the remote end or the period of
2637 * time that this port can pause the remote end.
2638 */
2616 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2617 PORT_PAUSE_CTRL, 0x0000);
2618 if (ret)
2619 return ret;
2639 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2640 if (err)
2641 return err;
2620
2621 /* Port ATU control: disable limiting the number of
2622 * address database entries that this port is allowed
2623 * to use.
2624 */
2642
2643 /* Port ATU control: disable limiting the number of
2644 * address database entries that this port is allowed
2645 * to use.
2646 */
2625 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2626 PORT_ATU_CONTROL, 0x0000);
2647 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2648 0x0000);
2627 /* Priority Override: disable DA, SA and VTU priority
2628 * override.
2629 */
2649 /* Priority Override: disable DA, SA and VTU priority
2650 * override.
2651 */
2630 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2631 PORT_PRI_OVERRIDE, 0x0000);
2632 if (ret)
2633 return ret;
2652 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2653 0x0000);
2654 if (err)
2655 return err;
2634
2635 /* Port Ethertype: use the Ethertype DSA Ethertype
2636 * value.
2637 */
2656
2657 /* Port Ethertype: use the Ethertype DSA Ethertype
2658 * value.
2659 */
2638 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2639 PORT_ETH_TYPE, ETH_P_EDSA);
2640 if (ret)
2641 return ret;
2660 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2661 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2662 ETH_P_EDSA);
2663 if (err)
2664 return err;
2665 }
2666
2642 /* Tag Remap: use an identity 802.1p prio -> switch
2643 * prio mapping.
2644 */
2667 /* Tag Remap: use an identity 802.1p prio -> switch
2668 * prio mapping.
2669 */
2645 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2646 PORT_TAG_REGMAP_0123, 0x3210);
2647 if (ret)
2648 return ret;
2670 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2671 0x3210);
2672 if (err)
2673 return err;
2649
2650 /* Tag Remap 2: use an identity 802.1p prio -> switch
2651 * prio mapping.
2652 */
2674
2675 /* Tag Remap 2: use an identity 802.1p prio -> switch
2676 * prio mapping.
2677 */
2653 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2654 PORT_TAG_REGMAP_4567, 0x7654);
2655 if (ret)
2656 return ret;
2678 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2679 0x7654);
2680 if (err)
2681 return err;
2657 }
2658
2659 /* Rate Control: disable ingress rate limiting. */
2660 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2661 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2662 mv88e6xxx_6320_family(chip)) {
2682 }
2683
2684 /* Rate Control: disable ingress rate limiting. */
2685 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2686 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2687 mv88e6xxx_6320_family(chip)) {
2663 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2664 PORT_RATE_CONTROL, 0x0001);
2665 if (ret)
2666 return ret;
2688 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2689 0x0001);
2690 if (err)
2691 return err;
2667 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2692 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2668 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2669 PORT_RATE_CONTROL, 0x0000);
2670 if (ret)
2671 return ret;
2693 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2694 0x0000);
2695 if (err)
2696 return err;
2672 }
2673
2674 /* Port Control 1: disable trunking, disable sending
2675 * learning messages to this port.
2676 */
2697 }
2698
2699 /* Port Control 1: disable trunking, disable sending
2700 * learning messages to this port.
2701 */
2677 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2678 0x0000);
2679 if (ret)
2680 return ret;
2702 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2703 if (err)
2704 return err;
2681
2682 /* Port based VLAN map: give each port the same default address
2683 * database, and allow bidirectional communication between the
2684 * CPU and DSA port(s), and the other ports.
2685 */
2705
2706 /* Port based VLAN map: give each port the same default address
2707 * database, and allow bidirectional communication between the
2708 * CPU and DSA port(s), and the other ports.
2709 */
2686 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2687 if (ret)
2688 return ret;
2710 err = _mv88e6xxx_port_fid_set(chip, port, 0);
2711 if (err)
2712 return err;
2689
2713
2690 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2691 if (ret)
2692 return ret;
2714 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2715 if (err)
2716 return err;
2693
2694 /* Default VLAN ID and priority: don't set a default VLAN
2695 * ID, and set the default packet priority to zero.
2696 */
2717
2718 /* Default VLAN ID and priority: don't set a default VLAN
2719 * ID, and set the default packet priority to zero.
2720 */
2697 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2698 0x0000);
2699 if (ret)
2700 return ret;
2701
2702 return 0;
2721 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2703}
2704
2722}
2723
2705static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2724int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2706{
2707 int err;
2708
2725{
2726 int err;
2727
2709 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2710 (addr[0] << 8) | addr[1]);
2728 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2711 if (err)
2712 return err;
2713
2729 if (err)
2730 return err;
2731
2714 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2715 (addr[2] << 8) | addr[3]);
2732 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2716 if (err)
2717 return err;
2718
2733 if (err)
2734 return err;
2735
2719 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2720 (addr[4] << 8) | addr[5]);
2736 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2737 if (err)
2738 return err;
2739
2740 return 0;
2721}
2722
2723static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2724 unsigned int msecs)
2725{
2726 const unsigned int coeff = chip->info->age_time_coeff;
2727 const unsigned int min = 0x01 * coeff;
2728 const unsigned int max = 0xff * coeff;
2729 u8 age_time;
2730 u16 val;
2731 int err;
2732
2733 if (msecs < min || msecs > max)
2734 return -ERANGE;
2735
2736 /* Round to nearest multiple of coeff */
2737 age_time = (msecs + coeff / 2) / coeff;
2738
2741}
2742
2743static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2744 unsigned int msecs)
2745{
2746 const unsigned int coeff = chip->info->age_time_coeff;
2747 const unsigned int min = 0x01 * coeff;
2748 const unsigned int max = 0xff * coeff;
2749 u8 age_time;
2750 u16 val;
2751 int err;
2752
2753 if (msecs < min || msecs > max)
2754 return -ERANGE;
2755
2756 /* Round to nearest multiple of coeff */
2757 age_time = (msecs + coeff / 2) / coeff;
2758
2739 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2759 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2740 if (err)
2741 return err;
2742
2743 /* AgeTime is 11:4 bits */
2744 val &= ~0xff0;
2745 val |= age_time << 4;
2746
2760 if (err)
2761 return err;
2762
2763 /* AgeTime is 11:4 bits */
2764 val &= ~0xff0;
2765 val |= age_time << 4;
2766
2747 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2767 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2748}
2749
2750static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2751 unsigned int ageing_time)
2752{
2768}
2769
2770static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2771 unsigned int ageing_time)
2772{
2753 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2773 struct mv88e6xxx_chip *chip = ds->priv;
2754 int err;
2755
2756 mutex_lock(&chip->reg_lock);
2757 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2758 mutex_unlock(&chip->reg_lock);
2759
2760 return err;
2761}

--- 8 unchanged lines hidden (view full) ---

2770 /* Enable the PHY Polling Unit if present, don't discard any packets,
2771 * and mask all interrupt sources.
2772 */
2773 reg = 0;
2774 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2775 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2776 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2777
2774 int err;
2775
2776 mutex_lock(&chip->reg_lock);
2777 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2778 mutex_unlock(&chip->reg_lock);
2779
2780 return err;
2781}

--- 8 unchanged lines hidden (view full) ---

2790 /* Enable the PHY Polling Unit if present, don't discard any packets,
2791 * and mask all interrupt sources.
2792 */
2793 reg = 0;
2794 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2795 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2796 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2797
2778 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2798 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
2779 if (err)
2780 return err;
2781
2782 /* Configure the upstream port, and configure it as the port to which
2783 * ingress and egress and ARP monitor frames are to be sent.
2784 */
2785 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2786 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2787 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2799 if (err)
2800 return err;
2801
2802 /* Configure the upstream port, and configure it as the port to which
2803 * ingress and egress and ARP monitor frames are to be sent.
2804 */
2805 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2806 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2807 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2788 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2789 reg);
2808 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
2790 if (err)
2791 return err;
2792
2793 /* Disable remote management, and set the switch's DSA device number. */
2809 if (err)
2810 return err;
2811
2812 /* Disable remote management, and set the switch's DSA device number. */
2794 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2795 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2796 (ds->index & 0x1f));
2813 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2814 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2815 (ds->index & 0x1f));
2797 if (err)
2798 return err;
2799
2800 /* Clear all the VTU and STU entries */
2801 err = _mv88e6xxx_vtu_stu_flush(chip);
2802 if (err < 0)
2803 return err;
2804
2805 /* Set the default address aging time to 5 minutes, and
2806 * enable address learn messages to be sent to all message
2807 * ports.
2808 */
2816 if (err)
2817 return err;
2818
2819 /* Clear all the VTU and STU entries */
2820 err = _mv88e6xxx_vtu_stu_flush(chip);
2821 if (err < 0)
2822 return err;
2823
2824 /* Set the default address aging time to 5 minutes, and
2825 * enable address learn messages to be sent to all message
2826 * ports.
2827 */
2809 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2810 GLOBAL_ATU_CONTROL_LEARN2ALL);
2828 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2829 GLOBAL_ATU_CONTROL_LEARN2ALL);
2811 if (err)
2812 return err;
2813
2814 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2815 if (err)
2816 return err;
2817
2818 /* Clear all ATU entries */
2819 err = _mv88e6xxx_atu_flush(chip, 0, true);
2820 if (err)
2821 return err;
2822
2823 /* Configure the IP ToS mapping registers. */
2830 if (err)
2831 return err;
2832
2833 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2834 if (err)
2835 return err;
2836
2837 /* Clear all ATU entries */
2838 err = _mv88e6xxx_atu_flush(chip, 0, true);
2839 if (err)
2840 return err;
2841
2842 /* Configure the IP ToS mapping registers. */
2824 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2843 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2825 if (err)
2826 return err;
2844 if (err)
2845 return err;
2827 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2846 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2828 if (err)
2829 return err;
2847 if (err)
2848 return err;
2830 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2849 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2831 if (err)
2832 return err;
2850 if (err)
2851 return err;
2833 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2852 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2834 if (err)
2835 return err;
2853 if (err)
2854 return err;
2836 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2855 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2837 if (err)
2838 return err;
2856 if (err)
2857 return err;
2839 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2858 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2840 if (err)
2841 return err;
2859 if (err)
2860 return err;
2842 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2861 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2843 if (err)
2844 return err;
2862 if (err)
2863 return err;
2845 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2864 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2846 if (err)
2847 return err;
2848
2849 /* Configure the IEEE 802.1p priority mapping register. */
2865 if (err)
2866 return err;
2867
2868 /* Configure the IEEE 802.1p priority mapping register. */
2850 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2869 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2851 if (err)
2852 return err;
2853
2854 /* Clear the statistics counters for all ports */
2870 if (err)
2871 return err;
2872
2873 /* Clear the statistics counters for all ports */
2855 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2856 GLOBAL_STATS_OP_FLUSH_ALL);
2874 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2875 GLOBAL_STATS_OP_FLUSH_ALL);
2857 if (err)
2858 return err;
2859
2860 /* Wait for the flush to complete. */
2861 err = _mv88e6xxx_stats_wait(chip);
2862 if (err)
2863 return err;
2864
2865 return 0;
2866}
2867
2876 if (err)
2877 return err;
2878
2879 /* Wait for the flush to complete. */
2880 err = _mv88e6xxx_stats_wait(chip);
2881 if (err)
2882 return err;
2883
2884 return 0;
2885}
2886
2868static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2869 int target, int port)
2870{
2871 u16 val = (target << 8) | (port & 0xf);
2872
2873 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2874}
2875
2876static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2877{
2878 int target, port;
2879 int err;
2880
2881 /* Initialize the routing port to the 32 possible target devices */
2882 for (target = 0; target < 32; ++target) {
2883 port = 0xf;
2884
2885 if (target < DSA_MAX_SWITCHES) {
2886 port = chip->ds->rtable[target];
2887 if (port == DSA_RTABLE_NONE)
2888 port = 0xf;
2889 }
2890
2891 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2892 if (err)
2893 break;
2894 }
2895
2896 return err;
2897}
2898
2899static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2900 bool hask, u16 mask)
2901{
2902 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2903 u16 val = (num << 12) | (mask & port_mask);
2904
2905 if (hask)
2906 val |= GLOBAL2_TRUNK_MASK_HASK;
2907
2908 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2909}
2910
2911static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2912 u16 map)
2913{
2914 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2915 u16 val = (id << 11) | (map & port_mask);
2916
2917 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2918}
2919
2920static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2921{
2922 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2923 int i, err;
2924
2925 /* Clear all eight possible Trunk Mask vectors */
2926 for (i = 0; i < 8; ++i) {
2927 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2928 if (err)
2929 return err;
2930 }
2931
2932 /* Clear all sixteen possible Trunk ID routing vectors */
2933 for (i = 0; i < 16; ++i) {
2934 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2935 if (err)
2936 return err;
2937 }
2938
2939 return 0;
2940}
2941
2942static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2943{
2944 int port, err;
2945
2946 /* Init all Ingress Rate Limit resources of all ports */
2947 for (port = 0; port < chip->info->num_ports; ++port) {
2948 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2949 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2950 GLOBAL2_IRL_CMD_OP_INIT_ALL |
2951 (port << 8));
2952 if (err)
2953 break;
2954
2955 /* Wait for the operation to complete */
2956 err = _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2957 GLOBAL2_IRL_CMD_BUSY);
2958 if (err)
2959 break;
2960 }
2961
2962 return err;
2963}
2964
2965/* Indirect write to the Switch MAC/WoL/WoF register */
2966static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2967 unsigned int pointer, u8 data)
2968{
2969 u16 val = (pointer << 8) | data;
2970
2971 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2972}
2973
2974static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2975{
2976 int i, err;
2977
2978 for (i = 0; i < 6; i++) {
2979 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2980 if (err)
2981 break;
2982 }
2983
2984 return err;
2985}
2986
2987static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2988 u8 data)
2989{
2990 u16 val = (pointer << 8) | (data & 0x7);
2991
2992 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2993}
2994
2995static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2996{
2997 int i, err;
2998
2999 /* Clear all sixteen possible Priority Override entries */
3000 for (i = 0; i < 16; i++) {
3001 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3002 if (err)
3003 break;
3004 }
3005
3006 return err;
3007}
3008
3009static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3010{
3011 return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3012 GLOBAL2_EEPROM_CMD_BUSY |
3013 GLOBAL2_EEPROM_CMD_RUNNING);
3014}
3015
3016static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3017{
3018 int err;
3019
3020 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3021 if (err)
3022 return err;
3023
3024 return mv88e6xxx_g2_eeprom_wait(chip);
3025}
3026
3027static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3028 u8 addr, u16 *data)
3029{
3030 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3031 int err;
3032
3033 err = mv88e6xxx_g2_eeprom_wait(chip);
3034 if (err)
3035 return err;
3036
3037 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3038 if (err)
3039 return err;
3040
3041 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3042}
3043
3044static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3045 u8 addr, u16 data)
3046{
3047 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3048 int err;
3049
3050 err = mv88e6xxx_g2_eeprom_wait(chip);
3051 if (err)
3052 return err;
3053
3054 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3055 if (err)
3056 return err;
3057
3058 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3059}
3060
3061static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3062{
3063 u16 reg;
3064 int err;
3065
3066 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3067 /* Consider the frames with reserved multicast destination
3068 * addresses matching 01:80:c2:00:00:2x as MGMT.
3069 */
3070 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3071 0xffff);
3072 if (err)
3073 return err;
3074 }
3075
3076 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3077 /* Consider the frames with reserved multicast destination
3078 * addresses matching 01:80:c2:00:00:0x as MGMT.
3079 */
3080 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3081 0xffff);
3082 if (err)
3083 return err;
3084 }
3085
3086 /* Ignore removed tag data on doubly tagged packets, disable
3087 * flow control messages, force flow control priority to the
3088 * highest, and send all special multicast frames to the CPU
3089 * port at the highest priority.
3090 */
3091 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3092 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3093 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3094 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3095 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3096 if (err)
3097 return err;
3098
3099 /* Program the DSA routing table. */
3100 err = mv88e6xxx_g2_set_device_mapping(chip);
3101 if (err)
3102 return err;
3103
3104 /* Clear all trunk masks and mapping. */
3105 err = mv88e6xxx_g2_clear_trunk(chip);
3106 if (err)
3107 return err;
3108
3109 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3110 /* Disable ingress rate limiting by resetting all per port
3111 * ingress rate limit resources to their initial state.
3112 */
3113 err = mv88e6xxx_g2_clear_irl(chip);
3114 if (err)
3115 return err;
3116 }
3117
3118 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3119 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3120 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3121 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3122 if (err)
3123 return err;
3124 }
3125
3126 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3127 /* Clear the priority override table. */
3128 err = mv88e6xxx_g2_clear_pot(chip);
3129 if (err)
3130 return err;
3131 }
3132
3133 return 0;
3134}
3135
3136static int mv88e6xxx_setup(struct dsa_switch *ds)
3137{
2887static int mv88e6xxx_setup(struct dsa_switch *ds)
2888{
3138 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2889 struct mv88e6xxx_chip *chip = ds->priv;
3139 int err;
3140 int i;
3141
3142 chip->ds = ds;
3143 ds->slave_mii_bus = chip->mdio_bus;
3144
3145 mutex_lock(&chip->reg_lock);
3146

--- 23 unchanged lines hidden (view full) ---

3170unlock:
3171 mutex_unlock(&chip->reg_lock);
3172
3173 return err;
3174}
3175
3176static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3177{
2890 int err;
2891 int i;
2892
2893 chip->ds = ds;
2894 ds->slave_mii_bus = chip->mdio_bus;
2895
2896 mutex_lock(&chip->reg_lock);
2897

--- 23 unchanged lines hidden (view full) ---

2921unlock:
2922 mutex_unlock(&chip->reg_lock);
2923
2924 return err;
2925}
2926
2927static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2928{
3178 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2929 struct mv88e6xxx_chip *chip = ds->priv;
3179 int err;
3180
3181 mutex_lock(&chip->reg_lock);
3182
3183 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3184 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3185 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3186 else
3187 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3188
3189 mutex_unlock(&chip->reg_lock);
3190
3191 return err;
3192}
3193
2930 int err;
2931
2932 mutex_lock(&chip->reg_lock);
2933
2934 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
2935 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
2936 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
2937 else
2938 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
2939
2940 mutex_unlock(&chip->reg_lock);
2941
2942 return err;
2943}
2944
3194#ifdef CONFIG_NET_DSA_HWMON
3195static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3196 int reg)
2945static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3197{
2946{
3198 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3199 int ret;
3200
3201 mutex_lock(&chip->reg_lock);
3202 ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3203 mutex_unlock(&chip->reg_lock);
3204
3205 return ret;
3206}
3207
3208static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3209 int reg, int val)
3210{
3211 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3212 int ret;
3213
3214 mutex_lock(&chip->reg_lock);
3215 ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3216 mutex_unlock(&chip->reg_lock);
3217
3218 return ret;
3219}
3220#endif
3221
3222static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3223{
3224 if (port >= 0 && port < chip->info->num_ports)
3225 return port;
3226 return -EINVAL;
3227}
3228
3229static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3230{
3231 struct mv88e6xxx_chip *chip = bus->priv;
2947 struct mv88e6xxx_chip *chip = bus->priv;
3232 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3233 int ret;
2948 u16 val;
2949 int err;
3234
2950
3235 if (addr < 0)
2951 if (phy >= chip->info->num_ports)
3236 return 0xffff;
3237
3238 mutex_lock(&chip->reg_lock);
2952 return 0xffff;
2953
2954 mutex_lock(&chip->reg_lock);
3239
3240 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3241 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3242 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3243 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3244 else
3245 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3246
2955 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
3247 mutex_unlock(&chip->reg_lock);
2956 mutex_unlock(&chip->reg_lock);
3248 return ret;
2957
2958 return err ? err : val;
3249}
3250
2959}
2960
3251static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3252 u16 val)
2961static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3253{
3254 struct mv88e6xxx_chip *chip = bus->priv;
2962{
2963 struct mv88e6xxx_chip *chip = bus->priv;
3255 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3256 int ret;
2964 int err;
3257
2965
3258 if (addr < 0)
2966 if (phy >= chip->info->num_ports)
3259 return 0xffff;
3260
3261 mutex_lock(&chip->reg_lock);
2967 return 0xffff;
2968
2969 mutex_lock(&chip->reg_lock);
3262
3263 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3264 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3265 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3266 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3267 else
3268 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3269
2970 err = mv88e6xxx_phy_write(chip, phy, reg, val);
3270 mutex_unlock(&chip->reg_lock);
2971 mutex_unlock(&chip->reg_lock);
3271 return ret;
2972
2973 return err;
3272}
3273
3274static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3275 struct device_node *np)
3276{
3277 static int index;
3278 struct mii_bus *bus;
3279 int err;
3280
2974}
2975
2976static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2977 struct device_node *np)
2978{
2979 static int index;
2980 struct mii_bus *bus;
2981 int err;
2982
3281 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3282 mv88e6xxx_ppu_state_init(chip);
3283
3284 if (np)
3285 chip->mdio_np = of_get_child_by_name(np, "mdio");
3286
3287 bus = devm_mdiobus_alloc(chip->dev);
3288 if (!bus)
3289 return -ENOMEM;
3290
3291 bus->priv = (void *)chip;

--- 38 unchanged lines hidden (view full) ---

3330 if (chip->mdio_np)
3331 of_node_put(chip->mdio_np);
3332}
3333
3334#ifdef CONFIG_NET_DSA_HWMON
3335
3336static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3337{
2983 if (np)
2984 chip->mdio_np = of_get_child_by_name(np, "mdio");
2985
2986 bus = devm_mdiobus_alloc(chip->dev);
2987 if (!bus)
2988 return -ENOMEM;
2989
2990 bus->priv = (void *)chip;

--- 38 unchanged lines hidden (view full) ---

3029 if (chip->mdio_np)
3030 of_node_put(chip->mdio_np);
3031}
3032
3033#ifdef CONFIG_NET_DSA_HWMON
3034
3035static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3036{
3338 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3037 struct mv88e6xxx_chip *chip = ds->priv;
3038 u16 val;
3339 int ret;
3039 int ret;
3340 int val;
3341
3342 *temp = 0;
3343
3344 mutex_lock(&chip->reg_lock);
3345
3040
3041 *temp = 0;
3042
3043 mutex_lock(&chip->reg_lock);
3044
3346 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3045 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3347 if (ret < 0)
3348 goto error;
3349
3350 /* Enable temperature sensor */
3046 if (ret < 0)
3047 goto error;
3048
3049 /* Enable temperature sensor */
3351 ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3050 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3352 if (ret < 0)
3353 goto error;
3354
3051 if (ret < 0)
3052 goto error;
3053
3355 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3054 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3356 if (ret < 0)
3357 goto error;
3358
3359 /* Wait for temperature to stabilize */
3360 usleep_range(10000, 12000);
3361
3055 if (ret < 0)
3056 goto error;
3057
3058 /* Wait for temperature to stabilize */
3059 usleep_range(10000, 12000);
3060
3362 val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3363 if (val < 0) {
3364 ret = val;
3061 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3062 if (ret < 0)
3365 goto error;
3063 goto error;
3366 }
3367
3368 /* Disable temperature sensor */
3064
3065 /* Disable temperature sensor */
3369 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3066 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3370 if (ret < 0)
3371 goto error;
3372
3373 *temp = ((val & 0x1f) - 5) * 5;
3374
3375error:
3067 if (ret < 0)
3068 goto error;
3069
3070 *temp = ((val & 0x1f) - 5) * 5;
3071
3072error:
3376 mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3073 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3377 mutex_unlock(&chip->reg_lock);
3378 return ret;
3379}
3380
3381static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3382{
3074 mutex_unlock(&chip->reg_lock);
3075 return ret;
3076}
3077
3078static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3079{
3383 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3080 struct mv88e6xxx_chip *chip = ds->priv;
3384 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3081 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3082 u16 val;
3385 int ret;
3386
3387 *temp = 0;
3388
3083 int ret;
3084
3085 *temp = 0;
3086
3389 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3087 mutex_lock(&chip->reg_lock);
3088 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3089 mutex_unlock(&chip->reg_lock);
3390 if (ret < 0)
3391 return ret;
3392
3090 if (ret < 0)
3091 return ret;
3092
3393 *temp = (ret & 0xff) - 25;
3093 *temp = (val & 0xff) - 25;
3394
3395 return 0;
3396}
3397
3398static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3399{
3094
3095 return 0;
3096}
3097
3098static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3099{
3400 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3100 struct mv88e6xxx_chip *chip = ds->priv;
3401
3402 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3403 return -EOPNOTSUPP;
3404
3405 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3406 return mv88e63xx_get_temp(ds, temp);
3407
3408 return mv88e61xx_get_temp(ds, temp);
3409}
3410
3411static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3412{
3101
3102 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3103 return -EOPNOTSUPP;
3104
3105 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3106 return mv88e63xx_get_temp(ds, temp);
3107
3108 return mv88e61xx_get_temp(ds, temp);
3109}
3110
3111static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3112{
3413 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3113 struct mv88e6xxx_chip *chip = ds->priv;
3414 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3114 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3115 u16 val;
3415 int ret;
3416
3417 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3418 return -EOPNOTSUPP;
3419
3420 *temp = 0;
3421
3116 int ret;
3117
3118 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3119 return -EOPNOTSUPP;
3120
3121 *temp = 0;
3122
3422 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3123 mutex_lock(&chip->reg_lock);
3124 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3125 mutex_unlock(&chip->reg_lock);
3423 if (ret < 0)
3424 return ret;
3425
3126 if (ret < 0)
3127 return ret;
3128
3426 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3129 *temp = (((val >> 8) & 0x1f) * 5) - 25;
3427
3428 return 0;
3429}
3430
3431static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3432{
3130
3131 return 0;
3132}
3133
3134static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3135{
3433 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3136 struct mv88e6xxx_chip *chip = ds->priv;
3434 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3137 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3435 int ret;
3138 u16 val;
3139 int err;
3436
3437 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3438 return -EOPNOTSUPP;
3439
3140
3141 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3142 return -EOPNOTSUPP;
3143
3440 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3441 if (ret < 0)
3442 return ret;
3144 mutex_lock(&chip->reg_lock);
3145 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3146 if (err)
3147 goto unlock;
3443 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3148 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3444 return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3445 (ret & 0xe0ff) | (temp << 8));
3149 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3150 (val & 0xe0ff) | (temp << 8));
3151unlock:
3152 mutex_unlock(&chip->reg_lock);
3153
3154 return err;
3446}
3447
3448static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3449{
3155}
3156
3157static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3158{
3450 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3159 struct mv88e6xxx_chip *chip = ds->priv;
3451 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3160 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3161 u16 val;
3452 int ret;
3453
3454 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3455 return -EOPNOTSUPP;
3456
3457 *alarm = false;
3458
3162 int ret;
3163
3164 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3165 return -EOPNOTSUPP;
3166
3167 *alarm = false;
3168
3459 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3169 mutex_lock(&chip->reg_lock);
3170 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3171 mutex_unlock(&chip->reg_lock);
3460 if (ret < 0)
3461 return ret;
3462
3172 if (ret < 0)
3173 return ret;
3174
3463 *alarm = !!(ret & 0x40);
3175 *alarm = !!(val & 0x40);
3464
3465 return 0;
3466}
3467#endif /* CONFIG_NET_DSA_HWMON */
3468
3469static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3470{
3176
3177 return 0;
3178}
3179#endif /* CONFIG_NET_DSA_HWMON */
3180
3181static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3182{
3471 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3183 struct mv88e6xxx_chip *chip = ds->priv;
3472
3473 return chip->eeprom_len;
3474}
3475
3184
3185 return chip->eeprom_len;
3186}
3187
3476static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3477 struct ethtool_eeprom *eeprom, u8 *data)
3478{
3479 unsigned int offset = eeprom->offset;
3480 unsigned int len = eeprom->len;
3481 u16 val;
3482 int err;
3483
3484 eeprom->len = 0;
3485
3486 if (offset & 1) {
3487 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3488 if (err)
3489 return err;
3490
3491 *data++ = (val >> 8) & 0xff;
3492
3493 offset++;
3494 len--;
3495 eeprom->len++;
3496 }
3497
3498 while (len >= 2) {
3499 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3500 if (err)
3501 return err;
3502
3503 *data++ = val & 0xff;
3504 *data++ = (val >> 8) & 0xff;
3505
3506 offset += 2;
3507 len -= 2;
3508 eeprom->len += 2;
3509 }
3510
3511 if (len) {
3512 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3513 if (err)
3514 return err;
3515
3516 *data++ = val & 0xff;
3517
3518 offset++;
3519 len--;
3520 eeprom->len++;
3521 }
3522
3523 return 0;
3524}
3525
3526static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3527 struct ethtool_eeprom *eeprom, u8 *data)
3528{
3188static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3189 struct ethtool_eeprom *eeprom, u8 *data)
3190{
3529 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3191 struct mv88e6xxx_chip *chip = ds->priv;
3530 int err;
3531
3532 mutex_lock(&chip->reg_lock);
3533
3534 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3192 int err;
3193
3194 mutex_lock(&chip->reg_lock);
3195
3196 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3535 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3197 err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data);
3536 else
3537 err = -EOPNOTSUPP;
3538
3539 mutex_unlock(&chip->reg_lock);
3540
3541 if (err)
3542 return err;
3543
3544 eeprom->magic = 0xc3ec4951;
3545
3546 return 0;
3547}
3548
3198 else
3199 err = -EOPNOTSUPP;
3200
3201 mutex_unlock(&chip->reg_lock);
3202
3203 if (err)
3204 return err;
3205
3206 eeprom->magic = 0xc3ec4951;
3207
3208 return 0;
3209}
3210
3549static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3550 struct ethtool_eeprom *eeprom, u8 *data)
3551{
3552 unsigned int offset = eeprom->offset;
3553 unsigned int len = eeprom->len;
3554 u16 val;
3555 int err;
3556
3557 /* Ensure the RO WriteEn bit is set */
3558 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3559 if (err)
3560 return err;
3561
3562 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3563 return -EROFS;
3564
3565 eeprom->len = 0;
3566
3567 if (offset & 1) {
3568 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3569 if (err)
3570 return err;
3571
3572 val = (*data++ << 8) | (val & 0xff);
3573
3574 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3575 if (err)
3576 return err;
3577
3578 offset++;
3579 len--;
3580 eeprom->len++;
3581 }
3582
3583 while (len >= 2) {
3584 val = *data++;
3585 val |= *data++ << 8;
3586
3587 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3588 if (err)
3589 return err;
3590
3591 offset += 2;
3592 len -= 2;
3593 eeprom->len += 2;
3594 }
3595
3596 if (len) {
3597 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3598 if (err)
3599 return err;
3600
3601 val = (val & 0xff00) | *data++;
3602
3603 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3604 if (err)
3605 return err;
3606
3607 offset++;
3608 len--;
3609 eeprom->len++;
3610 }
3611
3612 return 0;
3613}
3614
3615static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3616 struct ethtool_eeprom *eeprom, u8 *data)
3617{
3211static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3212 struct ethtool_eeprom *eeprom, u8 *data)
3213{
3618 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3214 struct mv88e6xxx_chip *chip = ds->priv;
3619 int err;
3620
3621 if (eeprom->magic != 0xc3ec4951)
3622 return -EINVAL;
3623
3624 mutex_lock(&chip->reg_lock);
3625
3626 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3215 int err;
3216
3217 if (eeprom->magic != 0xc3ec4951)
3218 return -EINVAL;
3219
3220 mutex_lock(&chip->reg_lock);
3221
3222 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3627 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3223 err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data);
3628 else
3629 err = -EOPNOTSUPP;
3630
3631 mutex_unlock(&chip->reg_lock);
3632
3633 return err;
3634}
3635
3636static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3637 [MV88E6085] = {
3638 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3639 .family = MV88E6XXX_FAMILY_6097,
3640 .name = "Marvell 88E6085",
3641 .num_databases = 4096,
3642 .num_ports = 10,
3643 .port_base_addr = 0x10,
3224 else
3225 err = -EOPNOTSUPP;
3226
3227 mutex_unlock(&chip->reg_lock);
3228
3229 return err;
3230}
3231
3232static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3233 [MV88E6085] = {
3234 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3235 .family = MV88E6XXX_FAMILY_6097,
3236 .name = "Marvell 88E6085",
3237 .num_databases = 4096,
3238 .num_ports = 10,
3239 .port_base_addr = 0x10,
3240 .global1_addr = 0x1b,
3644 .age_time_coeff = 15000,
3645 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3646 },
3647
3648 [MV88E6095] = {
3649 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3650 .family = MV88E6XXX_FAMILY_6095,
3651 .name = "Marvell 88E6095/88E6095F",
3652 .num_databases = 256,
3653 .num_ports = 11,
3654 .port_base_addr = 0x10,
3241 .age_time_coeff = 15000,
3242 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3243 },
3244
3245 [MV88E6095] = {
3246 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3247 .family = MV88E6XXX_FAMILY_6095,
3248 .name = "Marvell 88E6095/88E6095F",
3249 .num_databases = 256,
3250 .num_ports = 11,
3251 .port_base_addr = 0x10,
3252 .global1_addr = 0x1b,
3655 .age_time_coeff = 15000,
3656 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3657 },
3658
3659 [MV88E6123] = {
3660 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3661 .family = MV88E6XXX_FAMILY_6165,
3662 .name = "Marvell 88E6123",
3663 .num_databases = 4096,
3664 .num_ports = 3,
3665 .port_base_addr = 0x10,
3253 .age_time_coeff = 15000,
3254 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3255 },
3256
3257 [MV88E6123] = {
3258 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3259 .family = MV88E6XXX_FAMILY_6165,
3260 .name = "Marvell 88E6123",
3261 .num_databases = 4096,
3262 .num_ports = 3,
3263 .port_base_addr = 0x10,
3264 .global1_addr = 0x1b,
3666 .age_time_coeff = 15000,
3667 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3668 },
3669
3670 [MV88E6131] = {
3671 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3672 .family = MV88E6XXX_FAMILY_6185,
3673 .name = "Marvell 88E6131",
3674 .num_databases = 256,
3675 .num_ports = 8,
3676 .port_base_addr = 0x10,
3265 .age_time_coeff = 15000,
3266 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3267 },
3268
3269 [MV88E6131] = {
3270 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3271 .family = MV88E6XXX_FAMILY_6185,
3272 .name = "Marvell 88E6131",
3273 .num_databases = 256,
3274 .num_ports = 8,
3275 .port_base_addr = 0x10,
3276 .global1_addr = 0x1b,
3677 .age_time_coeff = 15000,
3678 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3679 },
3680
3681 [MV88E6161] = {
3682 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3683 .family = MV88E6XXX_FAMILY_6165,
3684 .name = "Marvell 88E6161",
3685 .num_databases = 4096,
3686 .num_ports = 6,
3687 .port_base_addr = 0x10,
3277 .age_time_coeff = 15000,
3278 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3279 },
3280
3281 [MV88E6161] = {
3282 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3283 .family = MV88E6XXX_FAMILY_6165,
3284 .name = "Marvell 88E6161",
3285 .num_databases = 4096,
3286 .num_ports = 6,
3287 .port_base_addr = 0x10,
3288 .global1_addr = 0x1b,
3688 .age_time_coeff = 15000,
3689 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3690 },
3691
3692 [MV88E6165] = {
3693 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3694 .family = MV88E6XXX_FAMILY_6165,
3695 .name = "Marvell 88E6165",
3696 .num_databases = 4096,
3697 .num_ports = 6,
3698 .port_base_addr = 0x10,
3289 .age_time_coeff = 15000,
3290 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3291 },
3292
3293 [MV88E6165] = {
3294 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3295 .family = MV88E6XXX_FAMILY_6165,
3296 .name = "Marvell 88E6165",
3297 .num_databases = 4096,
3298 .num_ports = 6,
3299 .port_base_addr = 0x10,
3300 .global1_addr = 0x1b,
3699 .age_time_coeff = 15000,
3700 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3701 },
3702
3703 [MV88E6171] = {
3704 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3705 .family = MV88E6XXX_FAMILY_6351,
3706 .name = "Marvell 88E6171",
3707 .num_databases = 4096,
3708 .num_ports = 7,
3709 .port_base_addr = 0x10,
3301 .age_time_coeff = 15000,
3302 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3303 },
3304
3305 [MV88E6171] = {
3306 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3307 .family = MV88E6XXX_FAMILY_6351,
3308 .name = "Marvell 88E6171",
3309 .num_databases = 4096,
3310 .num_ports = 7,
3311 .port_base_addr = 0x10,
3312 .global1_addr = 0x1b,
3710 .age_time_coeff = 15000,
3711 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3712 },
3713
3714 [MV88E6172] = {
3715 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3716 .family = MV88E6XXX_FAMILY_6352,
3717 .name = "Marvell 88E6172",
3718 .num_databases = 4096,
3719 .num_ports = 7,
3720 .port_base_addr = 0x10,
3313 .age_time_coeff = 15000,
3314 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3315 },
3316
3317 [MV88E6172] = {
3318 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3319 .family = MV88E6XXX_FAMILY_6352,
3320 .name = "Marvell 88E6172",
3321 .num_databases = 4096,
3322 .num_ports = 7,
3323 .port_base_addr = 0x10,
3324 .global1_addr = 0x1b,
3721 .age_time_coeff = 15000,
3722 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3723 },
3724
3725 [MV88E6175] = {
3726 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3727 .family = MV88E6XXX_FAMILY_6351,
3728 .name = "Marvell 88E6175",
3729 .num_databases = 4096,
3730 .num_ports = 7,
3731 .port_base_addr = 0x10,
3325 .age_time_coeff = 15000,
3326 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3327 },
3328
3329 [MV88E6175] = {
3330 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3331 .family = MV88E6XXX_FAMILY_6351,
3332 .name = "Marvell 88E6175",
3333 .num_databases = 4096,
3334 .num_ports = 7,
3335 .port_base_addr = 0x10,
3336 .global1_addr = 0x1b,
3732 .age_time_coeff = 15000,
3733 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3734 },
3735
3736 [MV88E6176] = {
3737 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3738 .family = MV88E6XXX_FAMILY_6352,
3739 .name = "Marvell 88E6176",
3740 .num_databases = 4096,
3741 .num_ports = 7,
3742 .port_base_addr = 0x10,
3337 .age_time_coeff = 15000,
3338 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3339 },
3340
3341 [MV88E6176] = {
3342 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3343 .family = MV88E6XXX_FAMILY_6352,
3344 .name = "Marvell 88E6176",
3345 .num_databases = 4096,
3346 .num_ports = 7,
3347 .port_base_addr = 0x10,
3348 .global1_addr = 0x1b,
3743 .age_time_coeff = 15000,
3744 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3745 },
3746
3747 [MV88E6185] = {
3748 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3749 .family = MV88E6XXX_FAMILY_6185,
3750 .name = "Marvell 88E6185",
3751 .num_databases = 256,
3752 .num_ports = 10,
3753 .port_base_addr = 0x10,
3349 .age_time_coeff = 15000,
3350 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3351 },
3352
3353 [MV88E6185] = {
3354 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3355 .family = MV88E6XXX_FAMILY_6185,
3356 .name = "Marvell 88E6185",
3357 .num_databases = 256,
3358 .num_ports = 10,
3359 .port_base_addr = 0x10,
3360 .global1_addr = 0x1b,
3754 .age_time_coeff = 15000,
3755 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3756 },
3757
3758 [MV88E6240] = {
3759 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3760 .family = MV88E6XXX_FAMILY_6352,
3761 .name = "Marvell 88E6240",
3762 .num_databases = 4096,
3763 .num_ports = 7,
3764 .port_base_addr = 0x10,
3361 .age_time_coeff = 15000,
3362 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3363 },
3364
3365 [MV88E6240] = {
3366 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3367 .family = MV88E6XXX_FAMILY_6352,
3368 .name = "Marvell 88E6240",
3369 .num_databases = 4096,
3370 .num_ports = 7,
3371 .port_base_addr = 0x10,
3372 .global1_addr = 0x1b,
3765 .age_time_coeff = 15000,
3766 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3767 },
3768
3769 [MV88E6320] = {
3770 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3771 .family = MV88E6XXX_FAMILY_6320,
3772 .name = "Marvell 88E6320",
3773 .num_databases = 4096,
3774 .num_ports = 7,
3775 .port_base_addr = 0x10,
3373 .age_time_coeff = 15000,
3374 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3375 },
3376
3377 [MV88E6320] = {
3378 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3379 .family = MV88E6XXX_FAMILY_6320,
3380 .name = "Marvell 88E6320",
3381 .num_databases = 4096,
3382 .num_ports = 7,
3383 .port_base_addr = 0x10,
3384 .global1_addr = 0x1b,
3776 .age_time_coeff = 15000,
3777 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3778 },
3779
3780 [MV88E6321] = {
3781 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3782 .family = MV88E6XXX_FAMILY_6320,
3783 .name = "Marvell 88E6321",
3784 .num_databases = 4096,
3785 .num_ports = 7,
3786 .port_base_addr = 0x10,
3385 .age_time_coeff = 15000,
3386 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3387 },
3388
3389 [MV88E6321] = {
3390 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3391 .family = MV88E6XXX_FAMILY_6320,
3392 .name = "Marvell 88E6321",
3393 .num_databases = 4096,
3394 .num_ports = 7,
3395 .port_base_addr = 0x10,
3396 .global1_addr = 0x1b,
3787 .age_time_coeff = 15000,
3788 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3789 },
3790
3791 [MV88E6350] = {
3792 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3793 .family = MV88E6XXX_FAMILY_6351,
3794 .name = "Marvell 88E6350",
3795 .num_databases = 4096,
3796 .num_ports = 7,
3797 .port_base_addr = 0x10,
3397 .age_time_coeff = 15000,
3398 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3399 },
3400
3401 [MV88E6350] = {
3402 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3403 .family = MV88E6XXX_FAMILY_6351,
3404 .name = "Marvell 88E6350",
3405 .num_databases = 4096,
3406 .num_ports = 7,
3407 .port_base_addr = 0x10,
3408 .global1_addr = 0x1b,
3798 .age_time_coeff = 15000,
3799 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3800 },
3801
3802 [MV88E6351] = {
3803 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3804 .family = MV88E6XXX_FAMILY_6351,
3805 .name = "Marvell 88E6351",
3806 .num_databases = 4096,
3807 .num_ports = 7,
3808 .port_base_addr = 0x10,
3409 .age_time_coeff = 15000,
3410 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3411 },
3412
3413 [MV88E6351] = {
3414 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3415 .family = MV88E6XXX_FAMILY_6351,
3416 .name = "Marvell 88E6351",
3417 .num_databases = 4096,
3418 .num_ports = 7,
3419 .port_base_addr = 0x10,
3420 .global1_addr = 0x1b,
3809 .age_time_coeff = 15000,
3810 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3811 },
3812
3813 [MV88E6352] = {
3814 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3815 .family = MV88E6XXX_FAMILY_6352,
3816 .name = "Marvell 88E6352",
3817 .num_databases = 4096,
3818 .num_ports = 7,
3819 .port_base_addr = 0x10,
3421 .age_time_coeff = 15000,
3422 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3423 },
3424
3425 [MV88E6352] = {
3426 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3427 .family = MV88E6XXX_FAMILY_6352,
3428 .name = "Marvell 88E6352",
3429 .num_databases = 4096,
3430 .num_ports = 7,
3431 .port_base_addr = 0x10,
3432 .global1_addr = 0x1b,
3820 .age_time_coeff = 15000,
3821 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3822 },
3823};
3824
3825static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3826{
3827 int i;

--- 23 unchanged lines hidden (view full) ---

3851
3852 info = mv88e6xxx_lookup_info(prod_num);
3853 if (!info)
3854 return -ENODEV;
3855
3856 /* Update the compatible info with the probed one */
3857 chip->info = info;
3858
3433 .age_time_coeff = 15000,
3434 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3435 },
3436};
3437
3438static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3439{
3440 int i;

--- 23 unchanged lines hidden (view full) ---

3464
3465 info = mv88e6xxx_lookup_info(prod_num);
3466 if (!info)
3467 return -ENODEV;
3468
3469 /* Update the compatible info with the probed one */
3470 chip->info = info;
3471
3472 err = mv88e6xxx_g2_require(chip);
3473 if (err)
3474 return err;
3475
3859 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3860 chip->info->prod_num, chip->info->name, rev);
3861
3862 return 0;
3863}
3864
3865static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3866{

--- 5 unchanged lines hidden (view full) ---

3872
3873 chip->dev = dev;
3874
3875 mutex_init(&chip->reg_lock);
3876
3877 return chip;
3878}
3879
3476 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3477 chip->info->prod_num, chip->info->name, rev);
3478
3479 return 0;
3480}
3481
3482static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3483{

--- 5 unchanged lines hidden (view full) ---

3489
3490 chip->dev = dev;
3491
3492 mutex_init(&chip->reg_lock);
3493
3494 return chip;
3495}
3496
3497static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3498 .read = mv88e6xxx_g2_smi_phy_read,
3499 .write = mv88e6xxx_g2_smi_phy_write,
3500};
3501
3502static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3503 .read = mv88e6xxx_read,
3504 .write = mv88e6xxx_write,
3505};
3506
3507static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3508{
3509 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3510 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3511 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3512 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3513 mv88e6xxx_ppu_state_init(chip);
3514 } else {
3515 chip->phy_ops = &mv88e6xxx_phy_ops;
3516 }
3517}
3518
3519static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3520{
3521 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3522 mv88e6xxx_ppu_state_destroy(chip);
3523 }
3524}
3525
3880static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3881 struct mii_bus *bus, int sw_addr)
3882{
3883 /* ADDR[0] pin is unavailable externally and considered zero */
3884 if (sw_addr & 0x1)
3885 return -EINVAL;
3886
3887 if (sw_addr == 0)
3888 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3526static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3527 struct mii_bus *bus, int sw_addr)
3528{
3529 /* ADDR[0] pin is unavailable externally and considered zero */
3530 if (sw_addr & 0x1)
3531 return -EINVAL;
3532
3533 if (sw_addr == 0)
3534 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3889 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3535 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3890 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3891 else
3892 return -EINVAL;
3893
3894 chip->bus = bus;
3895 chip->sw_addr = sw_addr;
3896
3897 return 0;
3898}
3899
3536 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3537 else
3538 return -EINVAL;
3539
3540 chip->bus = bus;
3541 chip->sw_addr = sw_addr;
3542
3543 return 0;
3544}
3545
3546static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3547{
3548 struct mv88e6xxx_chip *chip = ds->priv;
3549
3550 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3551 return DSA_TAG_PROTO_EDSA;
3552
3553 return DSA_TAG_PROTO_DSA;
3554}
3555
3900static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3901 struct device *host_dev, int sw_addr,
3902 void **priv)
3903{
3904 struct mv88e6xxx_chip *chip;
3905 struct mii_bus *bus;
3906 int err;
3907

--- 11 unchanged lines hidden (view full) ---

3919 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3920 if (err)
3921 goto free;
3922
3923 err = mv88e6xxx_detect(chip);
3924 if (err)
3925 goto free;
3926
3556static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3557 struct device *host_dev, int sw_addr,
3558 void **priv)
3559{
3560 struct mv88e6xxx_chip *chip;
3561 struct mii_bus *bus;
3562 int err;
3563

--- 11 unchanged lines hidden (view full) ---

3575 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3576 if (err)
3577 goto free;
3578
3579 err = mv88e6xxx_detect(chip);
3580 if (err)
3581 goto free;
3582
3583 mv88e6xxx_phy_init(chip);
3584
3927 err = mv88e6xxx_mdio_register(chip, NULL);
3928 if (err)
3929 goto free;
3930
3931 *priv = chip;
3932
3933 return chip->info->name;
3934free:
3935 devm_kfree(dsa_dev, chip);
3936
3937 return NULL;
3938}
3939
3585 err = mv88e6xxx_mdio_register(chip, NULL);
3586 if (err)
3587 goto free;
3588
3589 *priv = chip;
3590
3591 return chip->info->name;
3592free:
3593 devm_kfree(dsa_dev, chip);
3594
3595 return NULL;
3596}
3597
3940static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3941 .tag_protocol = DSA_TAG_PROTO_EDSA,
3598static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3599 const struct switchdev_obj_port_mdb *mdb,
3600 struct switchdev_trans *trans)
3601{
3602 /* We don't need any dynamic resource from the kernel (yet),
3603 * so skip the prepare phase.
3604 */
3605
3606 return 0;
3607}
3608
3609static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3610 const struct switchdev_obj_port_mdb *mdb,
3611 struct switchdev_trans *trans)
3612{
3613 struct mv88e6xxx_chip *chip = ds->priv;
3614
3615 mutex_lock(&chip->reg_lock);
3616 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3617 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3618 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3619 mutex_unlock(&chip->reg_lock);
3620}
3621
3622static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3623 const struct switchdev_obj_port_mdb *mdb)
3624{
3625 struct mv88e6xxx_chip *chip = ds->priv;
3626 int err;
3627
3628 mutex_lock(&chip->reg_lock);
3629 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3630 GLOBAL_ATU_DATA_STATE_UNUSED);
3631 mutex_unlock(&chip->reg_lock);
3632
3633 return err;
3634}
3635
3636static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3637 struct switchdev_obj_port_mdb *mdb,
3638 int (*cb)(struct switchdev_obj *obj))
3639{
3640 struct mv88e6xxx_chip *chip = ds->priv;
3641 int err;
3642
3643 mutex_lock(&chip->reg_lock);
3644 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3645 mutex_unlock(&chip->reg_lock);
3646
3647 return err;
3648}
3649
3650static struct dsa_switch_ops mv88e6xxx_switch_ops = {
3942 .probe = mv88e6xxx_drv_probe,
3651 .probe = mv88e6xxx_drv_probe,
3652 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3943 .setup = mv88e6xxx_setup,
3944 .set_addr = mv88e6xxx_set_addr,
3945 .adjust_link = mv88e6xxx_adjust_link,
3946 .get_strings = mv88e6xxx_get_strings,
3947 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3948 .get_sset_count = mv88e6xxx_get_sset_count,
3949 .set_eee = mv88e6xxx_set_eee,
3950 .get_eee = mv88e6xxx_get_eee,

--- 7 unchanged lines hidden (view full) ---

3958 .get_eeprom = mv88e6xxx_get_eeprom,
3959 .set_eeprom = mv88e6xxx_set_eeprom,
3960 .get_regs_len = mv88e6xxx_get_regs_len,
3961 .get_regs = mv88e6xxx_get_regs,
3962 .set_ageing_time = mv88e6xxx_set_ageing_time,
3963 .port_bridge_join = mv88e6xxx_port_bridge_join,
3964 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3965 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3653 .setup = mv88e6xxx_setup,
3654 .set_addr = mv88e6xxx_set_addr,
3655 .adjust_link = mv88e6xxx_adjust_link,
3656 .get_strings = mv88e6xxx_get_strings,
3657 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3658 .get_sset_count = mv88e6xxx_get_sset_count,
3659 .set_eee = mv88e6xxx_set_eee,
3660 .get_eee = mv88e6xxx_get_eee,

--- 7 unchanged lines hidden (view full) ---

3668 .get_eeprom = mv88e6xxx_get_eeprom,
3669 .set_eeprom = mv88e6xxx_set_eeprom,
3670 .get_regs_len = mv88e6xxx_get_regs_len,
3671 .get_regs = mv88e6xxx_get_regs,
3672 .set_ageing_time = mv88e6xxx_set_ageing_time,
3673 .port_bridge_join = mv88e6xxx_port_bridge_join,
3674 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3675 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3676 .port_fast_age = mv88e6xxx_port_fast_age,
3966 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3967 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3968 .port_vlan_add = mv88e6xxx_port_vlan_add,
3969 .port_vlan_del = mv88e6xxx_port_vlan_del,
3970 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3971 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3972 .port_fdb_add = mv88e6xxx_port_fdb_add,
3973 .port_fdb_del = mv88e6xxx_port_fdb_del,
3974 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3677 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3678 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3679 .port_vlan_add = mv88e6xxx_port_vlan_add,
3680 .port_vlan_del = mv88e6xxx_port_vlan_del,
3681 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3682 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3683 .port_fdb_add = mv88e6xxx_port_fdb_add,
3684 .port_fdb_del = mv88e6xxx_port_fdb_del,
3685 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3686 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3687 .port_mdb_add = mv88e6xxx_port_mdb_add,
3688 .port_mdb_del = mv88e6xxx_port_mdb_del,
3689 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
3975};
3976
3977static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3978 struct device_node *np)
3979{
3980 struct device *dev = chip->dev;
3981 struct dsa_switch *ds;
3982
3983 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3984 if (!ds)
3985 return -ENOMEM;
3986
3987 ds->dev = dev;
3988 ds->priv = chip;
3690};
3691
3692static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3693 struct device_node *np)
3694{
3695 struct device *dev = chip->dev;
3696 struct dsa_switch *ds;
3697
3698 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3699 if (!ds)
3700 return -ENOMEM;
3701
3702 ds->dev = dev;
3703 ds->priv = chip;
3989 ds->drv = &mv88e6xxx_switch_driver;
3704 ds->ops = &mv88e6xxx_switch_ops;
3990
3991 dev_set_drvdata(dev, ds);
3992
3993 return dsa_register_switch(ds, np);
3994}
3995
3996static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3997{

--- 22 unchanged lines hidden (view full) ---

4020 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4021 if (err)
4022 return err;
4023
4024 err = mv88e6xxx_detect(chip);
4025 if (err)
4026 return err;
4027
3705
3706 dev_set_drvdata(dev, ds);
3707
3708 return dsa_register_switch(ds, np);
3709}
3710
3711static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3712{

--- 22 unchanged lines hidden (view full) ---

3735 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3736 if (err)
3737 return err;
3738
3739 err = mv88e6xxx_detect(chip);
3740 if (err)
3741 return err;
3742
3743 mv88e6xxx_phy_init(chip);
3744
4028 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4029 if (IS_ERR(chip->reset))
4030 return PTR_ERR(chip->reset);
4031
4032 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4033 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4034 chip->eeprom_len = eeprom_len;
4035

--- 8 unchanged lines hidden (view full) ---

4044 }
4045
4046 return 0;
4047}
4048
4049static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4050{
4051 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3745 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3746 if (IS_ERR(chip->reset))
3747 return PTR_ERR(chip->reset);
3748
3749 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
3750 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3751 chip->eeprom_len = eeprom_len;
3752

--- 8 unchanged lines hidden (view full) ---

3761 }
3762
3763 return 0;
3764}
3765
3766static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3767{
3768 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4052 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3769 struct mv88e6xxx_chip *chip = ds->priv;
4053
3770
3771 mv88e6xxx_phy_destroy(chip);
4054 mv88e6xxx_unregister_switch(chip);
4055 mv88e6xxx_mdio_unregister(chip);
4056}
4057
4058static const struct of_device_id mv88e6xxx_of_match[] = {
4059 {
4060 .compatible = "marvell,mv88e6085",
4061 .data = &mv88e6xxx_table[MV88E6085],

--- 9 unchanged lines hidden (view full) ---

4071 .mdiodrv.driver = {
4072 .name = "mv88e6085",
4073 .of_match_table = mv88e6xxx_of_match,
4074 },
4075};
4076
4077static int __init mv88e6xxx_init(void)
4078{
3772 mv88e6xxx_unregister_switch(chip);
3773 mv88e6xxx_mdio_unregister(chip);
3774}
3775
3776static const struct of_device_id mv88e6xxx_of_match[] = {
3777 {
3778 .compatible = "marvell,mv88e6085",
3779 .data = &mv88e6xxx_table[MV88E6085],

--- 9 unchanged lines hidden (view full) ---

3789 .mdiodrv.driver = {
3790 .name = "mv88e6085",
3791 .of_match_table = mv88e6xxx_of_match,
3792 },
3793};
3794
3795static int __init mv88e6xxx_init(void)
3796{
4079 register_switch_driver(&mv88e6xxx_switch_driver);
3797 register_switch_driver(&mv88e6xxx_switch_ops);
4080 return mdio_driver_register(&mv88e6xxx_driver);
4081}
4082module_init(mv88e6xxx_init);
4083
4084static void __exit mv88e6xxx_cleanup(void)
4085{
4086 mdio_driver_unregister(&mv88e6xxx_driver);
3798 return mdio_driver_register(&mv88e6xxx_driver);
3799}
3800module_init(mv88e6xxx_init);
3801
3802static void __exit mv88e6xxx_cleanup(void)
3803{
3804 mdio_driver_unregister(&mv88e6xxx_driver);
4087 unregister_switch_driver(&mv88e6xxx_switch_driver);
3805 unregister_switch_driver(&mv88e6xxx_switch_ops);
4088}
4089module_exit(mv88e6xxx_cleanup);
4090
4091MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4092MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4093MODULE_LICENSE("GPL");
3806}
3807module_exit(mv88e6xxx_cleanup);
3808
3809MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3810MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3811MODULE_LICENSE("GPL");