ksz9477.c (d819524d3144f4703f45f473fdc85ad7579ae94c) ksz9477.c (2c119d9982b1aba54a2eca59c2455cd09f3bc749)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ9477 switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8#include <linux/kernel.h>

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188 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
189 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
190
191 /* disable interrupts */
192 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
193 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
194 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
195
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ9477 switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8#include <linux/kernel.h>

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188 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
189 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
190
191 /* disable interrupts */
192 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
193 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
194 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
195
196 /* KSZ9893 compatible chips do not support refclk configuration */
197 if (dev->chip_id == KSZ9893_CHIP_ID ||
198 dev->chip_id == KSZ8563_CHIP_ID)
199 return 0;
200
196 data8 = SW_ENABLE_REFCLKO;
197 if (dev->synclko_disable)
198 data8 = 0;
199 else if (dev->synclko_125)
200 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ;
201 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8);
202
203 return 0;

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259 mutex_lock(&mib->cnt_mutex);
260 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
261 MIB_COUNTER_FLUSH_FREEZE);
262 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
263 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
264 mutex_unlock(&mib->cnt_mutex);
265}
266
201 data8 = SW_ENABLE_REFCLKO;
202 if (dev->synclko_disable)
203 data8 = 0;
204 else if (dev->synclko_125)
205 data8 = SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ;
206 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, data8);
207
208 return 0;

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264 mutex_lock(&mib->cnt_mutex);
265 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
266 MIB_COUNTER_FLUSH_FREEZE);
267 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
268 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
269 mutex_unlock(&mib->cnt_mutex);
270}
271
267void ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
272static void ksz9477_r_phy_quirks(struct ksz_device *dev, u16 addr, u16 reg,
273 u16 *data)
268{
274{
275 /* KSZ8563R do not have extended registers but BMSR_ESTATEN and
276 * BMSR_ERCAP bits are set.
277 */
278 if (dev->chip_id == KSZ8563_CHIP_ID && reg == MII_BMSR)
279 *data &= ~(BMSR_ESTATEN | BMSR_ERCAP);
280}
281
282int ksz9477_r_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 *data)
283{
269 u16 val = 0xffff;
284 u16 val = 0xffff;
285 int ret;
270
271 /* No real PHY after this. Simulate the PHY.
272 * A fixed PHY can be setup in the device tree, but this function is
273 * still called for that port during initialization.
274 * For RGMII PHY there is no way to access it so the fixed PHY should
275 * be used. For SGMII PHY the supporting code will be added later.
276 */
286
287 /* No real PHY after this. Simulate the PHY.
288 * A fixed PHY can be setup in the device tree, but this function is
289 * still called for that port during initialization.
290 * For RGMII PHY there is no way to access it so the fixed PHY should
291 * be used. For SGMII PHY the supporting code will be added later.
292 */
277 if (addr >= dev->phy_port_cnt) {
293 if (!dev->info->internal_phy[addr]) {
278 struct ksz_port *p = &dev->ports[addr];
279
280 switch (reg) {
281 case MII_BMCR:
282 val = 0x1140;
283 break;
284 case MII_BMSR:
285 val = 0x796d;

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302 case MII_STAT1000:
303 if (p->phydev.speed == SPEED_1000)
304 val = 0x3800;
305 else
306 val = 0;
307 break;
308 }
309 } else {
294 struct ksz_port *p = &dev->ports[addr];
295
296 switch (reg) {
297 case MII_BMCR:
298 val = 0x1140;
299 break;
300 case MII_BMSR:
301 val = 0x796d;

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318 case MII_STAT1000:
319 if (p->phydev.speed == SPEED_1000)
320 val = 0x3800;
321 else
322 val = 0;
323 break;
324 }
325 } else {
310 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
326 ret = ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
327 if (ret)
328 return ret;
329
330 ksz9477_r_phy_quirks(dev, addr, reg, &val);
311 }
312
313 *data = val;
331 }
332
333 *data = val;
334
335 return 0;
314}
315
336}
337
316void ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
338int ksz9477_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val)
317{
318 /* No real PHY after this. */
339{
340 /* No real PHY after this. */
319 if (addr >= dev->phy_port_cnt)
320 return;
341 if (!dev->info->internal_phy[addr])
342 return 0;
321
343
322 /* No gigabit support. Do not write to this register. */
323 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
324 return;
325
326 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
344 return ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
327}
328
329void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member)
330{
331 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
332}
333
334void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)

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864 PORT_MIRROR_SNIFFER, false);
865}
866
867static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
868{
869 phy_interface_t interface;
870 bool gbit;
871
345}
346
347void ksz9477_cfg_port_member(struct ksz_device *dev, int port, u8 member)
348{
349 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
350}
351
352void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)

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882 PORT_MIRROR_SNIFFER, false);
883}
884
885static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
886{
887 phy_interface_t interface;
888 bool gbit;
889
872 if (port < dev->phy_port_cnt)
890 if (dev->info->internal_phy[port])
873 return PHY_INTERFACE_MODE_NA;
874
875 gbit = ksz_get_gbit(dev, port);
876
877 interface = ksz_get_xmii(dev, port, gbit);
878
879 return interface;
880}

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909 /* Transmit waveform amplitude can be improved
910 * (1000BASE-T, 100BASE-TX, 10BASE-Te)
911 */
912 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
913
914 /* Energy Efficient Ethernet (EEE) feature select must
915 * be manually disabled (except on KSZ8565 which is 100Mbit)
916 */
891 return PHY_INTERFACE_MODE_NA;
892
893 gbit = ksz_get_gbit(dev, port);
894
895 interface = ksz_get_xmii(dev, port, gbit);
896
897 return interface;
898}

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927 /* Transmit waveform amplitude can be improved
928 * (1000BASE-T, 100BASE-TX, 10BASE-Te)
929 */
930 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
931
932 /* Energy Efficient Ethernet (EEE) feature select must
933 * be manually disabled (except on KSZ8565 which is 100Mbit)
934 */
917 if (dev->features & GBIT_SUPPORT)
935 if (dev->info->gbit_capable[port])
918 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
919
920 /* Register settings are required to meet data sheet
921 * supply current specifications
922 */
923 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
924 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
925 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);

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936}
937
938void ksz9477_get_caps(struct ksz_device *dev, int port,
939 struct phylink_config *config)
940{
941 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE |
942 MAC_SYM_PAUSE;
943
936 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
937
938 /* Register settings are required to meet data sheet
939 * supply current specifications
940 */
941 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
942 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
943 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);

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954}
955
956void ksz9477_get_caps(struct ksz_device *dev, int port,
957 struct phylink_config *config)
958{
959 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE |
960 MAC_SYM_PAUSE;
961
944 if (dev->features & GBIT_SUPPORT)
962 if (dev->info->gbit_capable[port])
945 config->mac_capabilities |= MAC_1000FD;
946}
947
963 config->mac_capabilities |= MAC_1000FD;
964}
965
966int ksz9477_set_ageing_time(struct ksz_device *dev, unsigned int msecs)
967{
968 u32 secs = msecs / 1000;
969 u8 value;
970 u8 data;
971 int ret;
972
973 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs);
974
975 ret = ksz_write8(dev, REG_SW_LUE_CTRL_3, value);
976 if (ret < 0)
977 return ret;
978
979 data = FIELD_GET(SW_AGE_PERIOD_10_8_M, secs);
980
981 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value);
982 if (ret < 0)
983 return ret;
984
985 value &= ~SW_AGE_CNT_M;
986 value |= FIELD_PREP(SW_AGE_CNT_M, data);
987
988 return ksz_write8(dev, REG_SW_LUE_CTRL_0, value);
989}
990
948void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
949{
950 struct dsa_switch *ds = dev->ds;
951 u16 data16;
952 u8 member;
953
954 /* enable tag tail for host port */
955 if (cpu_port)

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971 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
972 false);
973 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
974 MTI_PVID_REPLACE, false);
975
976 /* enable 802.1p priority */
977 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
978
991void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
992{
993 struct dsa_switch *ds = dev->ds;
994 u16 data16;
995 u8 member;
996
997 /* enable tag tail for host port */
998 if (cpu_port)

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1014 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1015 false);
1016 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1017 MTI_PVID_REPLACE, false);
1018
1019 /* enable 802.1p priority */
1020 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1021
979 if (port < dev->phy_port_cnt) {
1022 if (dev->info->internal_phy[port]) {
980 /* do not force flow control */
981 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
982 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
983 false);
984
985 if (dev->info->phy_errata_9477)
986 ksz9477_phy_errata_setup(dev, port);
987 } else {

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994 if (cpu_port)
995 member = dsa_user_ports(ds);
996 else
997 member = BIT(dsa_upstream_port(ds, port));
998
999 ksz9477_cfg_port_member(dev, port, member);
1000
1001 /* clear pending interrupts */
1023 /* do not force flow control */
1024 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1025 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1026 false);
1027
1028 if (dev->info->phy_errata_9477)
1029 ksz9477_phy_errata_setup(dev, port);
1030 } else {

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1037 if (cpu_port)
1038 member = dsa_user_ports(ds);
1039 else
1040 member = BIT(dsa_upstream_port(ds, port));
1041
1042 ksz9477_cfg_port_member(dev, port, member);
1043
1044 /* clear pending interrupts */
1002 if (port < dev->phy_port_cnt)
1045 if (dev->info->internal_phy[port])
1003 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1004}
1005
1006void ksz9477_config_cpu_port(struct dsa_switch *ds)
1007{
1008 struct ksz_device *dev = ds->priv;
1009 struct ksz_port *p;
1010 int i;

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1046 "Port%d: using phy mode %s%s%s\n",
1047 i,
1048 phy_modes(p->interface),
1049 prev_msg,
1050 prev_mode);
1051
1052 /* enable cpu port */
1053 ksz9477_port_setup(dev, i, true);
1046 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1047}
1048
1049void ksz9477_config_cpu_port(struct dsa_switch *ds)
1050{
1051 struct ksz_device *dev = ds->priv;
1052 struct ksz_port *p;
1053 int i;

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1089 "Port%d: using phy mode %s%s%s\n",
1090 i,
1091 phy_modes(p->interface),
1092 prev_msg,
1093 prev_mode);
1094
1095 /* enable cpu port */
1096 ksz9477_port_setup(dev, i, true);
1054 p->on = 1;
1055 }
1056 }
1057
1058 for (i = 0; i < dev->info->port_cnt; i++) {
1059 if (i == dev->cpu_port)
1060 continue;
1097 }
1098 }
1099
1100 for (i = 0; i < dev->info->port_cnt; i++) {
1101 if (i == dev->cpu_port)
1102 continue;
1061 p = &dev->ports[i];
1062
1063 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1103 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1064 p->on = 1;
1065 if (i < dev->phy_port_cnt)
1066 p->phy = 1;
1067 if (dev->chip_id == 0x00947700 && i == 6) {
1068 p->sgmii = 1;
1069
1070 /* SGMII PHY detection code is not implemented yet. */
1071 p->phy = 0;
1072 }
1073 }
1074}
1075
1076int ksz9477_enable_stp_addr(struct ksz_device *dev)
1077{
1078 const u32 *masks;
1079 u32 data;
1080 int ret;

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1153 if (ret)
1154 return ret;
1155
1156 data8 &= ~SPI_AUTO_EDGE_DETECTION;
1157 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1158 if (ret)
1159 return ret;
1160
1104 }
1105}
1106
1107int ksz9477_enable_stp_addr(struct ksz_device *dev)
1108{
1109 const u32 *masks;
1110 u32 data;
1111 int ret;

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1184 if (ret)
1185 return ret;
1186
1187 data8 &= ~SPI_AUTO_EDGE_DETECTION;
1188 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1189 if (ret)
1190 return ret;
1191
1161 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1162 if (ret)
1163 return ret;
1164
1165 /* Number of ports can be reduced depending on chip. */
1166 dev->phy_port_cnt = 5;
1167
1168 /* Default capability is gigabit capable. */
1169 dev->features = GBIT_SUPPORT;
1170
1171 if (dev->chip_id == KSZ9893_CHIP_ID) {
1172 dev->features |= IS_9893;
1173
1174 /* Chip does not support gigabit. */
1175 if (data8 & SW_QW_ABLE)
1176 dev->features &= ~GBIT_SUPPORT;
1177 dev->phy_port_cnt = 2;
1178 } else {
1179 /* Chip does not support gigabit. */
1180 if (!(data8 & SW_GIGABIT_ABLE))
1181 dev->features &= ~GBIT_SUPPORT;
1182 }
1183
1184 return 0;
1185}
1186
1187void ksz9477_switch_exit(struct ksz_device *dev)
1188{
1189 ksz9477_reset_switch(dev);
1190}
1191
1192MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1193MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1194MODULE_LICENSE("GPL");
1192 return 0;
1193}
1194
1195void ksz9477_switch_exit(struct ksz_device *dev)
1196{
1197 ksz9477_reset_switch(dev);
1198}
1199
1200MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1201MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1202MODULE_LICENSE("GPL");