| sc520cdp.c (94bd217e2d683719ab21a4ac117d8a1b91cbedc9) | sc520cdp.c (3a9f76bdf365efdc869125f9f2386643007f997b) |
|---|---|
| 1/* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform 2 * 3 * Copyright (C) 2001 Sysgo Real-Time Solutions GmbH 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. --- 169 unchanged lines hidden (view full) --- 178 SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2), 179 WINDOW_ADDR_2_BIOS 180 } 181}; 182 183 184static void sc520cdp_setup_par(void) 185{ | 1/* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform 2 * 3 * Copyright (C) 2001 Sysgo Real-Time Solutions GmbH 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. --- 169 unchanged lines hidden (view full) --- 178 SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2), 179 WINDOW_ADDR_2_BIOS 180 } 181}; 182 183 184static void sc520cdp_setup_par(void) 185{ |
| 186 volatile unsigned long __iomem *mmcr; | 186 unsigned long __iomem *mmcr; |
| 187 unsigned long mmcr_val; 188 int i, j; 189 190 /* map in SC520's MMCR area */ 191 mmcr = ioremap_nocache(SC520_MMCR_BASE, SC520_MMCR_EXTENT); 192 if(!mmcr) { /* ioremap_nocache failed: skip the PAR reprogramming */ 193 /* force physical address fields to BIOS defaults: */ 194 for(i = 0; i < NUM_FLASH_BANKS; i++) 195 sc520cdp_map[i].phys = par_table[i].default_address; 196 return; 197 } 198 199 /* 200 ** Find the PARxx registers that are responsible for activating 201 ** ROMCS0, ROMCS1 and BOOTCS. Reprogram each of these with a 202 ** new value from the table. 203 */ 204 for(i = 0; i < NUM_FLASH_BANKS; i++) { /* for each par_table entry */ 205 for(j = 0; j < NUM_SC520_PAR; j++) { /* for each PAR register */ | 187 unsigned long mmcr_val; 188 int i, j; 189 190 /* map in SC520's MMCR area */ 191 mmcr = ioremap_nocache(SC520_MMCR_BASE, SC520_MMCR_EXTENT); 192 if(!mmcr) { /* ioremap_nocache failed: skip the PAR reprogramming */ 193 /* force physical address fields to BIOS defaults: */ 194 for(i = 0; i < NUM_FLASH_BANKS; i++) 195 sc520cdp_map[i].phys = par_table[i].default_address; 196 return; 197 } 198 199 /* 200 ** Find the PARxx registers that are responsible for activating 201 ** ROMCS0, ROMCS1 and BOOTCS. Reprogram each of these with a 202 ** new value from the table. 203 */ 204 for(i = 0; i < NUM_FLASH_BANKS; i++) { /* for each par_table entry */ 205 for(j = 0; j < NUM_SC520_PAR; j++) { /* for each PAR register */ |
| 206 mmcr_val = mmcr[SC520_PAR(j)]; | 206 mmcr_val = readl(&mmcr[SC520_PAR(j)]); |
| 207 /* if target device field matches, reprogram the PAR */ 208 if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev) 209 { | 207 /* if target device field matches, reprogram the PAR */ 208 if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev) 209 { |
| 210 mmcr[SC520_PAR(j)] = par_table[i].new_par; | 210 writel(par_table[i].new_par, &mmcr[SC520_PAR(j)]); |
| 211 break; 212 } 213 } 214 if(j == NUM_SC520_PAR) 215 { /* no matching PAR found: try default BIOS address */ 216 printk(KERN_NOTICE "Could not find PAR responsible for %s\n", 217 sc520cdp_map[i].name); 218 printk(KERN_NOTICE "Trying default address 0x%lx\n", --- 84 unchanged lines hidden --- | 211 break; 212 } 213 } 214 if(j == NUM_SC520_PAR) 215 { /* no matching PAR found: try default BIOS address */ 216 printk(KERN_NOTICE "Could not find PAR responsible for %s\n", 217 sc520cdp_map[i].name); 218 printk(KERN_NOTICE "Trying default address 0x%lx\n", --- 84 unchanged lines hidden --- |