sdhci.c (c9b74c5b8fb807187f6b1db09012828fcd2d7e73) sdhci.c (b8c86fc5d8deaa5a6dc49c2c1ed144e6838bf0f3)
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/highmem.h>
1/*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16#include <linux/delay.h>
17#include <linux/highmem.h>
18#include <linux/pci.h>
18#include <linux/io.h>
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21
22#include <linux/leds.h>
23
24#include <linux/mmc/host.h>
25
26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
29
30#define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
32
33static unsigned int debug_quirks = 0;
34
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21
22#include <linux/leds.h>
23
24#include <linux/mmc/host.h>
25
26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
29
30#define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
32
33static unsigned int debug_quirks = 0;
34
35/*
36 * Different quirks to handle when the hardware deviates from a strict
37 * interpretation of the SDHCI specification.
38 */
39
40/* Controller doesn't honor resets unless we touch the clock register */
41#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
42/* Controller has bad caps bits, but really supports DMA */
43#define SDHCI_QUIRK_FORCE_DMA (1<<1)
44/* Controller doesn't like to be reset when there is no card inserted. */
45#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
46/* Controller doesn't like clearing the power reg before a change */
47#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
48/* Controller has flaky internal state so reset it on each ios change */
49#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
50/* Controller has an unusable DMA engine */
51#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
52/* Controller can only DMA from 32-bit aligned addresses */
53#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
54/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
55#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
56/* Controller needs to be reset after each request to stay stable */
57#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
58/* Controller needs voltage and power writes to happen separately */
59#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<9)
60/* Controller has an off-by-one issue with timeout value */
61#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<10)
62
63static const struct pci_device_id pci_ids[] __devinitdata = {
64 {
65 .vendor = PCI_VENDOR_ID_RICOH,
66 .device = PCI_DEVICE_ID_RICOH_R5C822,
67 .subvendor = PCI_VENDOR_ID_IBM,
68 .subdevice = PCI_ANY_ID,
69 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
70 SDHCI_QUIRK_FORCE_DMA,
71 },
72
73 {
74 .vendor = PCI_VENDOR_ID_RICOH,
75 .device = PCI_DEVICE_ID_RICOH_R5C822,
76 .subvendor = PCI_VENDOR_ID_SAMSUNG,
77 .subdevice = PCI_ANY_ID,
78 .driver_data = SDHCI_QUIRK_FORCE_DMA |
79 SDHCI_QUIRK_NO_CARD_NO_RESET,
80 },
81
82 {
83 .vendor = PCI_VENDOR_ID_RICOH,
84 .device = PCI_DEVICE_ID_RICOH_R5C822,
85 .subvendor = PCI_ANY_ID,
86 .subdevice = PCI_ANY_ID,
87 .driver_data = SDHCI_QUIRK_FORCE_DMA,
88 },
89
90 {
91 .vendor = PCI_VENDOR_ID_TI,
92 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
93 .subvendor = PCI_ANY_ID,
94 .subdevice = PCI_ANY_ID,
95 .driver_data = SDHCI_QUIRK_FORCE_DMA,
96 },
97
98 {
99 .vendor = PCI_VENDOR_ID_ENE,
100 .device = PCI_DEVICE_ID_ENE_CB712_SD,
101 .subvendor = PCI_ANY_ID,
102 .subdevice = PCI_ANY_ID,
103 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
104 SDHCI_QUIRK_BROKEN_DMA,
105 },
106
107 {
108 .vendor = PCI_VENDOR_ID_ENE,
109 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
110 .subvendor = PCI_ANY_ID,
111 .subdevice = PCI_ANY_ID,
112 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
113 SDHCI_QUIRK_BROKEN_DMA,
114 },
115
116 {
117 .vendor = PCI_VENDOR_ID_ENE,
118 .device = PCI_DEVICE_ID_ENE_CB714_SD,
119 .subvendor = PCI_ANY_ID,
120 .subdevice = PCI_ANY_ID,
121 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
122 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
123 SDHCI_QUIRK_BROKEN_DMA,
124 },
125
126 {
127 .vendor = PCI_VENDOR_ID_ENE,
128 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
129 .subvendor = PCI_ANY_ID,
130 .subdevice = PCI_ANY_ID,
131 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
132 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
133 SDHCI_QUIRK_BROKEN_DMA,
134 },
135
136 {
137 .vendor = PCI_VENDOR_ID_MARVELL,
138 .device = PCI_DEVICE_ID_MARVELL_CAFE_SD,
139 .subvendor = PCI_ANY_ID,
140 .subdevice = PCI_ANY_ID,
141 .driver_data = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
142 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL,
143 },
144
145 {
146 .vendor = PCI_VENDOR_ID_JMICRON,
147 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
148 .subvendor = PCI_ANY_ID,
149 .subdevice = PCI_ANY_ID,
150 .driver_data = SDHCI_QUIRK_32BIT_DMA_ADDR |
151 SDHCI_QUIRK_32BIT_DMA_SIZE |
152 SDHCI_QUIRK_RESET_AFTER_REQUEST,
153 },
154
155 { /* Generic SD host controller */
156 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
157 },
158
159 { /* end: all zeroes */ },
160};
161
162MODULE_DEVICE_TABLE(pci, pci_ids);
163
164static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
165static void sdhci_finish_data(struct sdhci_host *);
166
167static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
168static void sdhci_finish_command(struct sdhci_host *);
169
170static void sdhci_dumpregs(struct sdhci_host *host)
171{

--- 38 unchanged lines hidden (view full) ---

210 * Low level functions *
211 * *
212\*****************************************************************************/
213
214static void sdhci_reset(struct sdhci_host *host, u8 mask)
215{
216 unsigned long timeout;
217
35static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
36static void sdhci_finish_data(struct sdhci_host *);
37
38static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
39static void sdhci_finish_command(struct sdhci_host *);
40
41static void sdhci_dumpregs(struct sdhci_host *host)
42{

--- 38 unchanged lines hidden (view full) ---

81 * Low level functions *
82 * *
83\*****************************************************************************/
84
85static void sdhci_reset(struct sdhci_host *host, u8 mask)
86{
87 unsigned long timeout;
88
218 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
89 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
219 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
220 SDHCI_CARD_PRESENT))
221 return;
222 }
223
224 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
225
226 if (mask & SDHCI_RESET_ALL)

--- 256 unchanged lines hidden (view full) ---

483 if (count >= 0xF)
484 break;
485 }
486
487 /*
488 * Compensate for an off-by-one error in the CaFe hardware; otherwise,
489 * a too-small count gives us interrupt timeouts.
490 */
90 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
91 SDHCI_CARD_PRESENT))
92 return;
93 }
94
95 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
96
97 if (mask & SDHCI_RESET_ALL)

--- 256 unchanged lines hidden (view full) ---

354 if (count >= 0xF)
355 break;
356 }
357
358 /*
359 * Compensate for an off-by-one error in the CaFe hardware; otherwise,
360 * a too-small count gives us interrupt timeouts.
361 */
491 if ((host->chip->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
362 if ((host->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL))
492 count++;
493
494 if (count >= 0xF) {
495 printk(KERN_WARNING "%s: Too large timeout requested!\n",
496 mmc_hostname(host->mmc));
497 count = 0xE;
498 }
499
500 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
501
502 if (host->flags & SDHCI_USE_DMA)
503 host->flags |= SDHCI_REQ_USE_DMA;
504
505 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
363 count++;
364
365 if (count >= 0xF) {
366 printk(KERN_WARNING "%s: Too large timeout requested!\n",
367 mmc_hostname(host->mmc));
368 count = 0xE;
369 }
370
371 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
372
373 if (host->flags & SDHCI_USE_DMA)
374 host->flags |= SDHCI_REQ_USE_DMA;
375
376 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
506 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
377 (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
507 ((data->blksz * data->blocks) & 0x3))) {
508 DBG("Reverting to PIO because of transfer size (%d)\n",
509 data->blksz * data->blocks);
510 host->flags &= ~SDHCI_REQ_USE_DMA;
511 }
512
513 /*
514 * The assumption here being that alignment is the same after
515 * translation to device address space.
516 */
517 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
378 ((data->blksz * data->blocks) & 0x3))) {
379 DBG("Reverting to PIO because of transfer size (%d)\n",
380 data->blksz * data->blocks);
381 host->flags &= ~SDHCI_REQ_USE_DMA;
382 }
383
384 /*
385 * The assumption here being that alignment is the same after
386 * translation to device address space.
387 */
388 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
518 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
389 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
519 (data->sg->offset & 0x3))) {
520 DBG("Reverting to PIO because of bad alignment\n");
521 host->flags &= ~SDHCI_REQ_USE_DMA;
522 }
523
524 if (host->flags & SDHCI_REQ_USE_DMA) {
525 int count;
526
390 (data->sg->offset & 0x3))) {
391 DBG("Reverting to PIO because of bad alignment\n");
392 host->flags &= ~SDHCI_REQ_USE_DMA;
393 }
394
395 if (host->flags & SDHCI_REQ_USE_DMA) {
396 int count;
397
527 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
528 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
529 BUG_ON(count != 1);
398 count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
399 (data->flags & MMC_DATA_READ) ?
400 DMA_FROM_DEVICE : DMA_TO_DEVICE);
401 WARN_ON(count != 1);
530
402
531 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
403 writel(sg_dma_address(data->sg),
404 host->ioaddr + SDHCI_DMA_ADDRESS);
532 } else {
533 host->cur_sg = data->sg;
534 host->num_sg = data->sg_len;
535
536 host->offset = 0;
537 host->remain = host->cur_sg->length;
538 }
539

--- 29 unchanged lines hidden (view full) ---

569 struct mmc_data *data;
570
571 BUG_ON(!host->data);
572
573 data = host->data;
574 host->data = NULL;
575
576 if (host->flags & SDHCI_REQ_USE_DMA) {
405 } else {
406 host->cur_sg = data->sg;
407 host->num_sg = data->sg_len;
408
409 host->offset = 0;
410 host->remain = host->cur_sg->length;
411 }
412

--- 29 unchanged lines hidden (view full) ---

442 struct mmc_data *data;
443
444 BUG_ON(!host->data);
445
446 data = host->data;
447 host->data = NULL;
448
449 if (host->flags & SDHCI_REQ_USE_DMA) {
577 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
578 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
450 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
451 (data->flags & MMC_DATA_READ) ?
452 DMA_FROM_DEVICE : DMA_TO_DEVICE);
579 }
580
581 /*
582 * The specification states that the block count register must
583 * be updated, but it does not specify at what point in the
584 * data flow. That makes the register entirely useless to read
585 * back so we have to assume that nothing made it to the card
586 * in the event of an error.

--- 178 unchanged lines hidden (view full) ---

765 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
766 goto out;
767 }
768
769 /*
770 * Spec says that we should clear the power reg before setting
771 * a new value. Some controllers don't seem to like this though.
772 */
453 }
454
455 /*
456 * The specification states that the block count register must
457 * be updated, but it does not specify at what point in the
458 * data flow. That makes the register entirely useless to read
459 * back so we have to assume that nothing made it to the card
460 * in the event of an error.

--- 178 unchanged lines hidden (view full) ---

639 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
640 goto out;
641 }
642
643 /*
644 * Spec says that we should clear the power reg before setting
645 * a new value. Some controllers don't seem to like this though.
646 */
773 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
647 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
774 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
775
776 pwr = SDHCI_POWER_ON;
777
778 switch (1 << power) {
779 case MMC_VDD_165_195:
780 pwr |= SDHCI_POWER_180;
781 break;

--- 8 unchanged lines hidden (view full) ---

790 default:
791 BUG();
792 }
793
794 /*
795 * At least the CaFe chip gets confused if we set the voltage
796 * and set turn on power at the same time, so set the voltage first.
797 */
648 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
649
650 pwr = SDHCI_POWER_ON;
651
652 switch (1 << power) {
653 case MMC_VDD_165_195:
654 pwr |= SDHCI_POWER_180;
655 break;

--- 8 unchanged lines hidden (view full) ---

664 default:
665 BUG();
666 }
667
668 /*
669 * At least the CaFe chip gets confused if we set the voltage
670 * and set turn on power at the same time, so set the voltage first.
671 */
798 if ((host->chip->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
672 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
799 writeb(pwr & ~SDHCI_POWER_ON,
800 host->ioaddr + SDHCI_POWER_CONTROL);
801
802 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
803
804out:
805 host->power = power;
806}

--- 71 unchanged lines hidden (view full) ---

878
879 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
880
881 /*
882 * Some (ENE) controllers go apeshit on some ios operation,
883 * signalling timeout and CRC errors even on CMD0. Resetting
884 * it on each ios seems to solve the problem.
885 */
673 writeb(pwr & ~SDHCI_POWER_ON,
674 host->ioaddr + SDHCI_POWER_CONTROL);
675
676 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
677
678out:
679 host->power = power;
680}

--- 71 unchanged lines hidden (view full) ---

752
753 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
754
755 /*
756 * Some (ENE) controllers go apeshit on some ios operation,
757 * signalling timeout and CRC errors even on CMD0. Resetting
758 * it on each ios seems to solve the problem.
759 */
886 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
760 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
887 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
888
889 mmiowb();
890 spin_unlock_irqrestore(&host->lock, flags);
891}
892
893static int sdhci_get_ro(struct mmc_host *mmc)
894{

--- 94 unchanged lines hidden (view full) ---

989
990 /*
991 * The controller needs a reset of internal state machines
992 * upon error conditions.
993 */
994 if (mrq->cmd->error ||
995 (mrq->data && (mrq->data->error ||
996 (mrq->data->stop && mrq->data->stop->error))) ||
761 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
762
763 mmiowb();
764 spin_unlock_irqrestore(&host->lock, flags);
765}
766
767static int sdhci_get_ro(struct mmc_host *mmc)
768{

--- 94 unchanged lines hidden (view full) ---

863
864 /*
865 * The controller needs a reset of internal state machines
866 * upon error conditions.
867 */
868 if (mrq->cmd->error ||
869 (mrq->data && (mrq->data->error ||
870 (mrq->data->stop && mrq->data->stop->error))) ||
997 (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
871 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
998
999 /* Some controllers need this kick or reset won't work here */
872
873 /* Some controllers need this kick or reset won't work here */
1000 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
874 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1001 unsigned int clock;
1002
1003 /* This is to force an update */
1004 clock = host->clock;
1005 host->clock = 0;
1006 sdhci_set_clock(host, clock);
1007 }
1008

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1224/*****************************************************************************\
1225 * *
1226 * Suspend/resume *
1227 * *
1228\*****************************************************************************/
1229
1230#ifdef CONFIG_PM
1231
875 unsigned int clock;
876
877 /* This is to force an update */
878 clock = host->clock;
879 host->clock = 0;
880 sdhci_set_clock(host, clock);
881 }
882

--- 215 unchanged lines hidden (view full) ---

1098/*****************************************************************************\
1099 * *
1100 * Suspend/resume *
1101 * *
1102\*****************************************************************************/
1103
1104#ifdef CONFIG_PM
1105
1232static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1106int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1233{
1107{
1234 struct sdhci_chip *chip;
1235 int i, ret;
1108 int ret;
1236
1109
1237 chip = pci_get_drvdata(pdev);
1238 if (!chip)
1239 return 0;
1110 ret = mmc_suspend_host(host->mmc, state);
1111 if (ret)
1112 return ret;
1240
1113
1241 DBG("Suspending...\n");
1114 free_irq(host->irq, host);
1242
1115
1243 for (i = 0;i < chip->num_slots;i++) {
1244 if (!chip->hosts[i])
1245 continue;
1246 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1247 if (ret) {
1248 for (i--;i >= 0;i--)
1249 mmc_resume_host(chip->hosts[i]->mmc);
1250 return ret;
1251 }
1252 }
1253
1254 pci_save_state(pdev);
1255 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1256
1257 for (i = 0;i < chip->num_slots;i++) {
1258 if (!chip->hosts[i])
1259 continue;
1260 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1261 }
1262
1263 pci_disable_device(pdev);
1264 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1265
1266 return 0;
1267}
1268
1116 return 0;
1117}
1118
1269static int sdhci_resume (struct pci_dev *pdev)
1119EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1120
1121int sdhci_resume_host(struct sdhci_host *host)
1270{
1122{
1271 struct sdhci_chip *chip;
1272 int i, ret;
1123 int ret;
1273
1124
1274 chip = pci_get_drvdata(pdev);
1275 if (!chip)
1276 return 0;
1125 if (host->flags & SDHCI_USE_DMA) {
1126 if (host->ops->enable_dma)
1127 host->ops->enable_dma(host);
1128 }
1277
1129
1278 DBG("Resuming...\n");
1279
1280 pci_set_power_state(pdev, PCI_D0);
1281 pci_restore_state(pdev);
1282 ret = pci_enable_device(pdev);
1130 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1131 mmc_hostname(host->mmc), host);
1283 if (ret)
1284 return ret;
1285
1132 if (ret)
1133 return ret;
1134
1286 for (i = 0;i < chip->num_slots;i++) {
1287 if (!chip->hosts[i])
1288 continue;
1289 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1290 pci_set_master(pdev);
1291 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1292 IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc),
1293 chip->hosts[i]);
1294 if (ret)
1295 return ret;
1296 sdhci_init(chip->hosts[i]);
1297 mmiowb();
1298 ret = mmc_resume_host(chip->hosts[i]->mmc);
1299 if (ret)
1300 return ret;
1301 }
1135 sdhci_init(host);
1136 mmiowb();
1302
1137
1138 ret = mmc_resume_host(host->mmc);
1139 if (ret)
1140 return ret;
1141
1303 return 0;
1304}
1305
1142 return 0;
1143}
1144
1306#else /* CONFIG_PM */
1145EXPORT_SYMBOL_GPL(sdhci_resume_host);
1307
1146
1308#define sdhci_suspend NULL
1309#define sdhci_resume NULL
1310
1311#endif /* CONFIG_PM */
1312
1313/*****************************************************************************\
1314 * *
1147#endif /* CONFIG_PM */
1148
1149/*****************************************************************************\
1150 * *
1315 * Device probing/removal *
1151 * Device allocation/registration *
1316 * *
1317\*****************************************************************************/
1318
1152 * *
1153\*****************************************************************************/
1154
1319static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1155struct sdhci_host *sdhci_alloc_host(struct device *dev,
1156 size_t priv_size)
1320{
1157{
1321 int ret;
1322 unsigned int version;
1323 struct sdhci_chip *chip;
1324 struct mmc_host *mmc;
1325 struct sdhci_host *host;
1326
1158 struct mmc_host *mmc;
1159 struct sdhci_host *host;
1160
1327 u8 first_bar;
1328 unsigned int caps;
1161 WARN_ON(dev == NULL);
1329
1162
1330 chip = pci_get_drvdata(pdev);
1331 BUG_ON(!chip);
1332
1333 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1334 if (ret)
1335 return ret;
1336
1337 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1338
1339 if (first_bar > 5) {
1340 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1341 return -ENODEV;
1342 }
1343
1344 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1345 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1346 return -ENODEV;
1347 }
1348
1349 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1350 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1351 "You may experience problems.\n");
1352 }
1353
1354 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1355 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1356 return -ENODEV;
1357 }
1358
1359 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1360 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1361 return -ENODEV;
1362 }
1363
1364 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1163 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1365 if (!mmc)
1164 if (!mmc)
1366 return -ENOMEM;
1165 return ERR_PTR(-ENOMEM);
1367
1368 host = mmc_priv(mmc);
1369 host->mmc = mmc;
1370
1166
1167 host = mmc_priv(mmc);
1168 host->mmc = mmc;
1169
1371 host->chip = chip;
1372 chip->hosts[slot] = host;
1170 return host;
1171}
1373
1172
1374 host->bar = first_bar + slot;
1173EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1375
1174
1376 host->addr = pci_resource_start(pdev, host->bar);
1377 host->irq = pdev->irq;
1175int sdhci_add_host(struct sdhci_host *host)
1176{
1177 struct mmc_host *mmc;
1178 unsigned int caps;
1179 unsigned int version;
1180 int ret;
1378
1181
1379 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1182 WARN_ON(host == NULL);
1183 if (host == NULL)
1184 return -EINVAL;
1380
1185
1381 ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc));
1382 if (ret)
1383 goto free;
1186 mmc = host->mmc;
1384
1187
1385 host->ioaddr = ioremap_nocache(host->addr,
1386 pci_resource_len(pdev, host->bar));
1387 if (!host->ioaddr) {
1388 ret = -ENOMEM;
1389 goto release;
1390 }
1188 if (debug_quirks)
1189 host->quirks = debug_quirks;
1391
1392 sdhci_reset(host, SDHCI_RESET_ALL);
1393
1394 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1395 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1396 if (version > 1) {
1397 printk(KERN_ERR "%s: Unknown controller version (%d). "
1398 "You may experience problems.\n", mmc_hostname(mmc),
1399 version);
1400 }
1401
1402 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1403
1190
1191 sdhci_reset(host, SDHCI_RESET_ALL);
1192
1193 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1194 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1195 if (version > 1) {
1196 printk(KERN_ERR "%s: Unknown controller version (%d). "
1197 "You may experience problems.\n", mmc_hostname(mmc),
1198 version);
1199 }
1200
1201 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1202
1404 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1203 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1405 host->flags |= SDHCI_USE_DMA;
1406 else if (!(caps & SDHCI_CAN_DO_DMA))
1407 DBG("Controller doesn't have DMA capability\n");
1408 else
1409 host->flags |= SDHCI_USE_DMA;
1410
1204 host->flags |= SDHCI_USE_DMA;
1205 else if (!(caps & SDHCI_CAN_DO_DMA))
1206 DBG("Controller doesn't have DMA capability\n");
1207 else
1208 host->flags |= SDHCI_USE_DMA;
1209
1411 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1210 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1412 (host->flags & SDHCI_USE_DMA)) {
1413 DBG("Disabling DMA as it is marked broken\n");
1414 host->flags &= ~SDHCI_USE_DMA;
1415 }
1416
1211 (host->flags & SDHCI_USE_DMA)) {
1212 DBG("Disabling DMA as it is marked broken\n");
1213 host->flags &= ~SDHCI_USE_DMA;
1214 }
1215
1417 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1418 (host->flags & SDHCI_USE_DMA)) {
1419 printk(KERN_WARNING "%s: Will use DMA "
1420 "mode even though HW doesn't fully "
1421 "claim to support it.\n", mmc_hostname(mmc));
1422 }
1423
1424 if (host->flags & SDHCI_USE_DMA) {
1216 if (host->flags & SDHCI_USE_DMA) {
1425 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1426 printk(KERN_WARNING "%s: No suitable DMA available. "
1427 "Falling back to PIO.\n", mmc_hostname(mmc));
1428 host->flags &= ~SDHCI_USE_DMA;
1217 if (host->ops->enable_dma) {
1218 if (host->ops->enable_dma(host)) {
1219 printk(KERN_WARNING "%s: No suitable DMA "
1220 "available. Falling back to PIO.\n",
1221 mmc_hostname(mmc));
1222 host->flags &= ~SDHCI_USE_DMA;
1223 }
1429 }
1430 }
1431
1224 }
1225 }
1226
1432 if (host->flags & SDHCI_USE_DMA)
1433 pci_set_master(pdev);
1434 else /* XXX: Hack to get MMC layer to avoid highmem */
1435 pdev->dma_mask = 0;
1227 /* XXX: Hack to get MMC layer to avoid highmem */
1228 if (!(host->flags & SDHCI_USE_DMA))
1229 mmc_dev(host->mmc)->dma_mask = 0;
1436
1437 host->max_clk =
1438 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1439 if (host->max_clk == 0) {
1440 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1441 "frequency.\n", mmc_hostname(mmc));
1230
1231 host->max_clk =
1232 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1233 if (host->max_clk == 0) {
1234 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1235 "frequency.\n", mmc_hostname(mmc));
1442 ret = -ENODEV;
1443 goto unmap;
1236 return -ENODEV;
1444 }
1445 host->max_clk *= 1000000;
1446
1447 host->timeout_clk =
1448 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1449 if (host->timeout_clk == 0) {
1450 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1451 "frequency.\n", mmc_hostname(mmc));
1237 }
1238 host->max_clk *= 1000000;
1239
1240 host->timeout_clk =
1241 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1242 if (host->timeout_clk == 0) {
1243 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1244 "frequency.\n", mmc_hostname(mmc));
1452 ret = -ENODEV;
1453 goto unmap;
1245 return -ENODEV;
1454 }
1455 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1456 host->timeout_clk *= 1000;
1457
1458 /*
1459 * Set host parameters.
1460 */
1461 mmc->ops = &sdhci_ops;

--- 10 unchanged lines hidden (view full) ---

1472 if (caps & SDHCI_CAN_VDD_300)
1473 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1474 if (caps & SDHCI_CAN_VDD_180)
1475 mmc->ocr_avail |= MMC_VDD_165_195;
1476
1477 if (mmc->ocr_avail == 0) {
1478 printk(KERN_ERR "%s: Hardware doesn't report any "
1479 "support voltages.\n", mmc_hostname(mmc));
1246 }
1247 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1248 host->timeout_clk *= 1000;
1249
1250 /*
1251 * Set host parameters.
1252 */
1253 mmc->ops = &sdhci_ops;

--- 10 unchanged lines hidden (view full) ---

1264 if (caps & SDHCI_CAN_VDD_300)
1265 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1266 if (caps & SDHCI_CAN_VDD_180)
1267 mmc->ocr_avail |= MMC_VDD_165_195;
1268
1269 if (mmc->ocr_avail == 0) {
1270 printk(KERN_ERR "%s: Hardware doesn't report any "
1271 "support voltages.\n", mmc_hostname(mmc));
1480 ret = -ENODEV;
1481 goto unmap;
1272 return -ENODEV;
1482 }
1483
1484 spin_lock_init(&host->lock);
1485
1486 /*
1487 * Maximum number of segments. Hardware cannot do scatter lists.
1488 */
1489 if (host->flags & SDHCI_USE_DMA)

--- 53 unchanged lines hidden (view full) ---

1543#endif
1544
1545#ifdef CONFIG_LEDS_CLASS
1546 host->led.name = mmc_hostname(mmc);
1547 host->led.brightness = LED_OFF;
1548 host->led.default_trigger = mmc_hostname(mmc);
1549 host->led.brightness_set = sdhci_led_control;
1550
1273 }
1274
1275 spin_lock_init(&host->lock);
1276
1277 /*
1278 * Maximum number of segments. Hardware cannot do scatter lists.
1279 */
1280 if (host->flags & SDHCI_USE_DMA)

--- 53 unchanged lines hidden (view full) ---

1334#endif
1335
1336#ifdef CONFIG_LEDS_CLASS
1337 host->led.name = mmc_hostname(mmc);
1338 host->led.brightness = LED_OFF;
1339 host->led.default_trigger = mmc_hostname(mmc);
1340 host->led.brightness_set = sdhci_led_control;
1341
1551 ret = led_classdev_register(&pdev->dev, &host->led);
1342 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1552 if (ret)
1553 goto reset;
1554#endif
1555
1556 mmiowb();
1557
1558 mmc_add_host(mmc);
1559
1343 if (ret)
1344 goto reset;
1345#endif
1346
1347 mmiowb();
1348
1349 mmc_add_host(mmc);
1350
1560 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n",
1561 mmc_hostname(mmc), host->addr, host->irq,
1351 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1352 mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
1562 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1563
1564 return 0;
1565
1566#ifdef CONFIG_LEDS_CLASS
1567reset:
1568 sdhci_reset(host, SDHCI_RESET_ALL);
1569 free_irq(host->irq, host);
1570#endif
1571untasklet:
1572 tasklet_kill(&host->card_tasklet);
1573 tasklet_kill(&host->finish_tasklet);
1353 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1354
1355 return 0;
1356
1357#ifdef CONFIG_LEDS_CLASS
1358reset:
1359 sdhci_reset(host, SDHCI_RESET_ALL);
1360 free_irq(host->irq, host);
1361#endif
1362untasklet:
1363 tasklet_kill(&host->card_tasklet);
1364 tasklet_kill(&host->finish_tasklet);
1574unmap:
1575 iounmap(host->ioaddr);
1576release:
1577 pci_release_region(pdev, host->bar);
1578free:
1579 mmc_free_host(mmc);
1580
1581 return ret;
1582}
1583
1365
1366 return ret;
1367}
1368
1584static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1369EXPORT_SYMBOL_GPL(sdhci_add_host);
1370
1371void sdhci_remove_host(struct sdhci_host *host)
1585{
1372{
1586 struct sdhci_chip *chip;
1587 struct mmc_host *mmc;
1588 struct sdhci_host *host;
1373 mmc_remove_host(host->mmc);
1589
1374
1590 chip = pci_get_drvdata(pdev);
1591 host = chip->hosts[slot];
1592 mmc = host->mmc;
1593
1594 chip->hosts[slot] = NULL;
1595
1596 mmc_remove_host(mmc);
1597
1598#ifdef CONFIG_LEDS_CLASS
1599 led_classdev_unregister(&host->led);
1600#endif
1601
1602 sdhci_reset(host, SDHCI_RESET_ALL);
1603
1604 free_irq(host->irq, host);
1605
1606 del_timer_sync(&host->timer);
1607
1608 tasklet_kill(&host->card_tasklet);
1609 tasklet_kill(&host->finish_tasklet);
1375#ifdef CONFIG_LEDS_CLASS
1376 led_classdev_unregister(&host->led);
1377#endif
1378
1379 sdhci_reset(host, SDHCI_RESET_ALL);
1380
1381 free_irq(host->irq, host);
1382
1383 del_timer_sync(&host->timer);
1384
1385 tasklet_kill(&host->card_tasklet);
1386 tasklet_kill(&host->finish_tasklet);
1610
1611 iounmap(host->ioaddr);
1612
1613 pci_release_region(pdev, host->bar);
1614
1615 mmc_free_host(mmc);
1616}
1617
1387}
1388
1618static int __devinit sdhci_probe(struct pci_dev *pdev,
1619 const struct pci_device_id *ent)
1620{
1621 int ret, i;
1622 u8 slots, rev;
1623 struct sdhci_chip *chip;
1389EXPORT_SYMBOL_GPL(sdhci_remove_host);
1624
1390
1625 BUG_ON(pdev == NULL);
1626 BUG_ON(ent == NULL);
1627
1628 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1629
1630 printk(KERN_INFO DRIVER_NAME
1631 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1632 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1633 (int)rev);
1634
1635 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1636 if (ret)
1637 return ret;
1638
1639 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1640 DBG("found %d slot(s)\n", slots);
1641 if (slots == 0)
1642 return -ENODEV;
1643
1644 ret = pci_enable_device(pdev);
1645 if (ret)
1646 return ret;
1647
1648 chip = kzalloc(sizeof(struct sdhci_chip) +
1649 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1650 if (!chip) {
1651 ret = -ENOMEM;
1652 goto err;
1653 }
1654
1655 chip->pdev = pdev;
1656 chip->quirks = ent->driver_data;
1657
1658 if (debug_quirks)
1659 chip->quirks = debug_quirks;
1660
1661 chip->num_slots = slots;
1662 pci_set_drvdata(pdev, chip);
1663
1664 for (i = 0;i < slots;i++) {
1665 ret = sdhci_probe_slot(pdev, i);
1666 if (ret) {
1667 for (i--;i >= 0;i--)
1668 sdhci_remove_slot(pdev, i);
1669 goto free;
1670 }
1671 }
1672
1673 return 0;
1674
1675free:
1676 pci_set_drvdata(pdev, NULL);
1677 kfree(chip);
1678
1679err:
1680 pci_disable_device(pdev);
1681 return ret;
1682}
1683
1684static void __devexit sdhci_remove(struct pci_dev *pdev)
1391void sdhci_free_host(struct sdhci_host *host)
1685{
1392{
1686 int i;
1687 struct sdhci_chip *chip;
1688
1689 chip = pci_get_drvdata(pdev);
1690
1691 if (chip) {
1692 for (i = 0;i < chip->num_slots;i++)
1693 sdhci_remove_slot(pdev, i);
1694
1695 pci_set_drvdata(pdev, NULL);
1696
1697 kfree(chip);
1698 }
1699
1700 pci_disable_device(pdev);
1393 mmc_free_host(host->mmc);
1701}
1702
1394}
1395
1703static struct pci_driver sdhci_driver = {
1704 .name = DRIVER_NAME,
1705 .id_table = pci_ids,
1706 .probe = sdhci_probe,
1707 .remove = __devexit_p(sdhci_remove),
1708 .suspend = sdhci_suspend,
1709 .resume = sdhci_resume,
1710};
1396EXPORT_SYMBOL_GPL(sdhci_free_host);
1711
1712/*****************************************************************************\
1713 * *
1714 * Driver init/exit *
1715 * *
1716\*****************************************************************************/
1717
1718static int __init sdhci_drv_init(void)
1719{
1720 printk(KERN_INFO DRIVER_NAME
1721 ": Secure Digital Host Controller Interface driver\n");
1722 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1723
1397
1398/*****************************************************************************\
1399 * *
1400 * Driver init/exit *
1401 * *
1402\*****************************************************************************/
1403
1404static int __init sdhci_drv_init(void)
1405{
1406 printk(KERN_INFO DRIVER_NAME
1407 ": Secure Digital Host Controller Interface driver\n");
1408 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1409
1724 return pci_register_driver(&sdhci_driver);
1410 return 0;
1725}
1726
1727static void __exit sdhci_drv_exit(void)
1728{
1411}
1412
1413static void __exit sdhci_drv_exit(void)
1414{
1729 DBG("Exiting\n");
1730
1731 pci_unregister_driver(&sdhci_driver);
1732}
1733
1734module_init(sdhci_drv_init);
1735module_exit(sdhci_drv_exit);
1736
1737module_param(debug_quirks, uint, 0444);
1738
1739MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1415}
1416
1417module_init(sdhci_drv_init);
1418module_exit(sdhci_drv_exit);
1419
1420module_param(debug_quirks, uint, 0444);
1421
1422MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1740MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1423MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1741MODULE_LICENSE("GPL");
1742
1743MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
1424MODULE_LICENSE("GPL");
1425
1426MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");