mxcmmc.c (70aa6109597ea6955a93f16430b588b5ee5ba547) | mxcmmc.c (c7ceab02543f8a03b4df3d4465b089c8117a5e09) |
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1/* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * --- 27 unchanged lines hidden (view full) --- 36#include <linux/types.h> 37#include <linux/of.h> 38#include <linux/of_device.h> 39#include <linux/of_dma.h> 40#include <linux/of_gpio.h> 41 42#include <asm/dma.h> 43#include <asm/irq.h> | 1/* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * --- 27 unchanged lines hidden (view full) --- 36#include <linux/types.h> 37#include <linux/of.h> 38#include <linux/of_device.h> 39#include <linux/of_dma.h> 40#include <linux/of_gpio.h> 41 42#include <asm/dma.h> 43#include <asm/irq.h> |
44#include <asm/sizes.h> | |
45#include <linux/platform_data/mmc-mxcmmc.h> 46 47#include <linux/platform_data/dma-imx.h> 48 49#define DRIVER_NAME "mxc-mmc" 50#define MXCMCI_TIMEOUT_MS 10000 51 52#define MMC_REG_STR_STP_CLK 0x00 --- 61 unchanged lines hidden (view full) --- 114#define INT_BUF_WRITE_EN (1 << 3) 115#define INT_END_CMD_RES_EN (1 << 2) 116#define INT_WRITE_OP_DONE_EN (1 << 1) 117#define INT_READ_OP_EN (1 << 0) 118 119enum mxcmci_type { 120 IMX21_MMC, 121 IMX31_MMC, | 44#include <linux/platform_data/mmc-mxcmmc.h> 45 46#include <linux/platform_data/dma-imx.h> 47 48#define DRIVER_NAME "mxc-mmc" 49#define MXCMCI_TIMEOUT_MS 10000 50 51#define MMC_REG_STR_STP_CLK 0x00 --- 61 unchanged lines hidden (view full) --- 113#define INT_BUF_WRITE_EN (1 << 3) 114#define INT_END_CMD_RES_EN (1 << 2) 115#define INT_WRITE_OP_DONE_EN (1 << 1) 116#define INT_READ_OP_EN (1 << 0) 117 118enum mxcmci_type { 119 IMX21_MMC, 120 IMX31_MMC, |
121 MPC512X_MMC, |
|
122}; 123 124struct mxcmci_host { 125 struct mmc_host *mmc; 126 struct resource *res; 127 void __iomem *base; 128 int irq; 129 int detect_irq; --- 37 unchanged lines hidden (view full) --- 167static struct platform_device_id mxcmci_devtype[] = { 168 { 169 .name = "imx21-mmc", 170 .driver_data = IMX21_MMC, 171 }, { 172 .name = "imx31-mmc", 173 .driver_data = IMX31_MMC, 174 }, { | 122}; 123 124struct mxcmci_host { 125 struct mmc_host *mmc; 126 struct resource *res; 127 void __iomem *base; 128 int irq; 129 int detect_irq; --- 37 unchanged lines hidden (view full) --- 167static struct platform_device_id mxcmci_devtype[] = { 168 { 169 .name = "imx21-mmc", 170 .driver_data = IMX21_MMC, 171 }, { 172 .name = "imx31-mmc", 173 .driver_data = IMX31_MMC, 174 }, { |
175 .name = "mpc512x-sdhc", 176 .driver_data = MPC512X_MMC, 177 }, { |
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175 /* sentinel */ 176 } 177}; 178MODULE_DEVICE_TABLE(platform, mxcmci_devtype); 179 180static const struct of_device_id mxcmci_of_match[] = { 181 { 182 .compatible = "fsl,imx21-mmc", 183 .data = &mxcmci_devtype[IMX21_MMC], 184 }, { 185 .compatible = "fsl,imx31-mmc", 186 .data = &mxcmci_devtype[IMX31_MMC], 187 }, { | 178 /* sentinel */ 179 } 180}; 181MODULE_DEVICE_TABLE(platform, mxcmci_devtype); 182 183static const struct of_device_id mxcmci_of_match[] = { 184 { 185 .compatible = "fsl,imx21-mmc", 186 .data = &mxcmci_devtype[IMX21_MMC], 187 }, { 188 .compatible = "fsl,imx31-mmc", 189 .data = &mxcmci_devtype[IMX31_MMC], 190 }, { |
191 .compatible = "fsl,mpc5121-sdhc", 192 .data = &mxcmci_devtype[MPC512X_MMC], 193 }, { |
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188 /* sentinel */ 189 } 190}; 191MODULE_DEVICE_TABLE(of, mxcmci_of_match); 192 193static inline int is_imx31_mmc(struct mxcmci_host *host) 194{ 195 return host->devtype == IMX31_MMC; 196} 197 | 194 /* sentinel */ 195 } 196}; 197MODULE_DEVICE_TABLE(of, mxcmci_of_match); 198 199static inline int is_imx31_mmc(struct mxcmci_host *host) 200{ 201 return host->devtype == IMX31_MMC; 202} 203 |
204static inline int is_mpc512x_mmc(struct mxcmci_host *host) 205{ 206 return host->devtype == MPC512X_MMC; 207} 208 209static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg) 210{ 211 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 212 return ioread32be(host->base + reg); 213 else 214 return readl(host->base + reg); 215} 216 217static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg) 218{ 219 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 220 iowrite32be(val, host->base + reg); 221 else 222 writel(val, host->base + reg); 223} 224 225static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg) 226{ 227 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 228 return ioread32be(host->base + reg); 229 else 230 return readw(host->base + reg); 231} 232 233static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) 234{ 235 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 236 iowrite32be(val, host->base + reg); 237 else 238 writew(val, host->base + reg); 239} 240 |
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198static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 199 200static inline void mxcmci_init_ocr(struct mxcmci_host *host) 201{ 202 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); 203 204 if (IS_ERR(host->vcc)) { 205 host->vcc = NULL; --- 35 unchanged lines hidden (view full) --- 241 242static void mxcmci_softreset(struct mxcmci_host *host) 243{ 244 int i; 245 246 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 247 248 /* reset sequence */ | 241static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 242 243static inline void mxcmci_init_ocr(struct mxcmci_host *host) 244{ 245 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); 246 247 if (IS_ERR(host->vcc)) { 248 host->vcc = NULL; --- 35 unchanged lines hidden (view full) --- 284 285static void mxcmci_softreset(struct mxcmci_host *host) 286{ 287 int i; 288 289 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 290 291 /* reset sequence */ |
249 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 250 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 251 host->base + MMC_REG_STR_STP_CLK); | 292 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK); 293 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 294 MMC_REG_STR_STP_CLK); |
252 253 for (i = 0; i < 8; i++) | 295 296 for (i = 0; i < 8; i++) |
254 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); | 297 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); |
255 | 298 |
256 writew(0xff, host->base + MMC_REG_RES_TO); | 299 mxcmci_writew(host, 0xff, MMC_REG_RES_TO); |
257} 258static int mxcmci_setup_dma(struct mmc_host *mmc); 259 260static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 261{ 262 unsigned int nob = data->blocks; 263 unsigned int blksz = data->blksz; 264 unsigned int datasize = nob * blksz; 265 struct scatterlist *sg; 266 enum dma_transfer_direction slave_dirn; 267 int i, nents; 268 269 if (data->flags & MMC_DATA_STREAM) 270 nob = 0xffff; 271 272 host->data = data; 273 data->bytes_xfered = 0; 274 | 300} 301static int mxcmci_setup_dma(struct mmc_host *mmc); 302 303static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 304{ 305 unsigned int nob = data->blocks; 306 unsigned int blksz = data->blksz; 307 unsigned int datasize = nob * blksz; 308 struct scatterlist *sg; 309 enum dma_transfer_direction slave_dirn; 310 int i, nents; 311 312 if (data->flags & MMC_DATA_STREAM) 313 nob = 0xffff; 314 315 host->data = data; 316 data->bytes_xfered = 0; 317 |
275 writew(nob, host->base + MMC_REG_NOB); 276 writew(blksz, host->base + MMC_REG_BLK_LEN); | 318 mxcmci_writew(host, nob, MMC_REG_NOB); 319 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN); |
277 host->datasize = datasize; 278 279 if (!mxcmci_use_dma(host)) 280 return 0; 281 282 for_each_sg(data->sg, sg, data->sg_len, i) { 283 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) { 284 host->do_dma = 0; --- 39 unchanged lines hidden (view full) --- 324 325static void mxcmci_dma_callback(void *data) 326{ 327 struct mxcmci_host *host = data; 328 u32 stat; 329 330 del_timer(&host->watchdog); 331 | 320 host->datasize = datasize; 321 322 if (!mxcmci_use_dma(host)) 323 return 0; 324 325 for_each_sg(data->sg, sg, data->sg_len, i) { 326 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) { 327 host->do_dma = 0; --- 39 unchanged lines hidden (view full) --- 367 368static void mxcmci_dma_callback(void *data) 369{ 370 struct mxcmci_host *host = data; 371 u32 stat; 372 373 del_timer(&host->watchdog); 374 |
332 stat = readl(host->base + MMC_REG_STATUS); 333 writel(stat & ~STATUS_DATA_TRANS_DONE, host->base + MMC_REG_STATUS); | 375 stat = mxcmci_readl(host, MMC_REG_STATUS); 376 mxcmci_writel(host, stat & ~STATUS_DATA_TRANS_DONE, MMC_REG_STATUS); |
334 335 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 336 337 if (stat & STATUS_READ_OP_DONE) | 377 378 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 379 380 if (stat & STATUS_READ_OP_DONE) |
338 writel(STATUS_READ_OP_DONE, host->base + MMC_REG_STATUS); | 381 mxcmci_writel(host, STATUS_READ_OP_DONE, MMC_REG_STATUS); |
339 340 mxcmci_data_done(host, stat); 341} 342 343static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 344 unsigned int cmdat) 345{ 346 u32 int_cntr = host->default_irq_mask; --- 31 unchanged lines hidden (view full) --- 378 } else { 379 int_cntr |= INT_WRITE_OP_DONE_EN; 380 } 381 } 382 383 spin_lock_irqsave(&host->lock, flags); 384 if (host->use_sdio) 385 int_cntr |= INT_SDIO_IRQ_EN; | 382 383 mxcmci_data_done(host, stat); 384} 385 386static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 387 unsigned int cmdat) 388{ 389 u32 int_cntr = host->default_irq_mask; --- 31 unchanged lines hidden (view full) --- 421 } else { 422 int_cntr |= INT_WRITE_OP_DONE_EN; 423 } 424 } 425 426 spin_lock_irqsave(&host->lock, flags); 427 if (host->use_sdio) 428 int_cntr |= INT_SDIO_IRQ_EN; |
386 writel(int_cntr, host->base + MMC_REG_INT_CNTR); | 429 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); |
387 spin_unlock_irqrestore(&host->lock, flags); 388 | 430 spin_unlock_irqrestore(&host->lock, flags); 431 |
389 writew(cmd->opcode, host->base + MMC_REG_CMD); 390 writel(cmd->arg, host->base + MMC_REG_ARG); 391 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); | 432 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD); 433 mxcmci_writel(host, cmd->arg, MMC_REG_ARG); 434 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT); |
392 393 return 0; 394} 395 396static void mxcmci_finish_request(struct mxcmci_host *host, 397 struct mmc_request *req) 398{ 399 u32 int_cntr = host->default_irq_mask; 400 unsigned long flags; 401 402 spin_lock_irqsave(&host->lock, flags); 403 if (host->use_sdio) 404 int_cntr |= INT_SDIO_IRQ_EN; | 435 436 return 0; 437} 438 439static void mxcmci_finish_request(struct mxcmci_host *host, 440 struct mmc_request *req) 441{ 442 u32 int_cntr = host->default_irq_mask; 443 unsigned long flags; 444 445 spin_lock_irqsave(&host->lock, flags); 446 if (host->use_sdio) 447 int_cntr |= INT_SDIO_IRQ_EN; |
405 writel(int_cntr, host->base + MMC_REG_INT_CNTR); | 448 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); |
406 spin_unlock_irqrestore(&host->lock, flags); 407 408 host->req = NULL; 409 host->cmd = NULL; 410 host->data = NULL; 411 412 mmc_request_done(host->mmc, req); 413} --- 58 unchanged lines hidden (view full) --- 472 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 473 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 474 cmd->error = -EILSEQ; 475 } 476 477 if (cmd->flags & MMC_RSP_PRESENT) { 478 if (cmd->flags & MMC_RSP_136) { 479 for (i = 0; i < 4; i++) { | 449 spin_unlock_irqrestore(&host->lock, flags); 450 451 host->req = NULL; 452 host->cmd = NULL; 453 host->data = NULL; 454 455 mmc_request_done(host->mmc, req); 456} --- 58 unchanged lines hidden (view full) --- 515 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 516 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 517 cmd->error = -EILSEQ; 518 } 519 520 if (cmd->flags & MMC_RSP_PRESENT) { 521 if (cmd->flags & MMC_RSP_136) { 522 for (i = 0; i < 4; i++) { |
480 a = readw(host->base + MMC_REG_RES_FIFO); 481 b = readw(host->base + MMC_REG_RES_FIFO); | 523 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 524 b = mxcmci_readw(host, MMC_REG_RES_FIFO); |
482 cmd->resp[i] = a << 16 | b; 483 } 484 } else { | 525 cmd->resp[i] = a << 16 | b; 526 } 527 } else { |
485 a = readw(host->base + MMC_REG_RES_FIFO); 486 b = readw(host->base + MMC_REG_RES_FIFO); 487 c = readw(host->base + MMC_REG_RES_FIFO); | 528 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 529 b = mxcmci_readw(host, MMC_REG_RES_FIFO); 530 c = mxcmci_readw(host, MMC_REG_RES_FIFO); |
488 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 489 } 490 } 491} 492 493static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 494{ 495 u32 stat; 496 unsigned long timeout = jiffies + HZ; 497 498 do { | 531 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 532 } 533 } 534} 535 536static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 537{ 538 u32 stat; 539 unsigned long timeout = jiffies + HZ; 540 541 do { |
499 stat = readl(host->base + MMC_REG_STATUS); | 542 stat = mxcmci_readl(host, MMC_REG_STATUS); |
500 if (stat & STATUS_ERR_MASK) 501 return stat; 502 if (time_after(jiffies, timeout)) { 503 mxcmci_softreset(host); 504 mxcmci_set_clk_rate(host, host->clock); 505 return STATUS_TIME_OUT_READ; 506 } 507 if (stat & mask) --- 7 unchanged lines hidden (view full) --- 515 unsigned int stat; 516 u32 *buf = _buf; 517 518 while (bytes > 3) { 519 stat = mxcmci_poll_status(host, 520 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 521 if (stat) 522 return stat; | 543 if (stat & STATUS_ERR_MASK) 544 return stat; 545 if (time_after(jiffies, timeout)) { 546 mxcmci_softreset(host); 547 mxcmci_set_clk_rate(host, host->clock); 548 return STATUS_TIME_OUT_READ; 549 } 550 if (stat & mask) --- 7 unchanged lines hidden (view full) --- 558 unsigned int stat; 559 u32 *buf = _buf; 560 561 while (bytes > 3) { 562 stat = mxcmci_poll_status(host, 563 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 564 if (stat) 565 return stat; |
523 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS); | 566 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); |
524 bytes -= 4; 525 } 526 527 if (bytes) { 528 u8 *b = (u8 *)buf; 529 u32 tmp; 530 531 stat = mxcmci_poll_status(host, 532 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 533 if (stat) 534 return stat; | 567 bytes -= 4; 568 } 569 570 if (bytes) { 571 u8 *b = (u8 *)buf; 572 u32 tmp; 573 574 stat = mxcmci_poll_status(host, 575 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 576 if (stat) 577 return stat; |
535 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS); | 578 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); |
536 memcpy(b, &tmp, bytes); 537 } 538 539 return 0; 540} 541 542static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 543{ 544 unsigned int stat; 545 u32 *buf = _buf; 546 547 while (bytes > 3) { 548 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 549 if (stat) 550 return stat; | 579 memcpy(b, &tmp, bytes); 580 } 581 582 return 0; 583} 584 585static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 586{ 587 unsigned int stat; 588 u32 *buf = _buf; 589 590 while (bytes > 3) { 591 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 592 if (stat) 593 return stat; |
551 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS); | 594 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS); |
552 bytes -= 4; 553 } 554 555 if (bytes) { 556 u8 *b = (u8 *)buf; 557 u32 tmp; 558 559 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 560 if (stat) 561 return stat; 562 563 memcpy(&tmp, b, bytes); | 595 bytes -= 4; 596 } 597 598 if (bytes) { 599 u8 *b = (u8 *)buf; 600 u32 tmp; 601 602 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 603 if (stat) 604 return stat; 605 606 memcpy(&tmp, b, bytes); |
564 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS); | 607 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS); |
565 } 566 567 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 568 if (stat) 569 return stat; 570 571 return 0; 572} --- 29 unchanged lines hidden (view full) --- 602} 603 604static void mxcmci_datawork(struct work_struct *work) 605{ 606 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 607 datawork); 608 int datastat = mxcmci_transfer_data(host); 609 | 608 } 609 610 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 611 if (stat) 612 return stat; 613 614 return 0; 615} --- 29 unchanged lines hidden (view full) --- 645} 646 647static void mxcmci_datawork(struct work_struct *work) 648{ 649 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 650 datawork); 651 int datastat = mxcmci_transfer_data(host); 652 |
610 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 611 host->base + MMC_REG_STATUS); | 653 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 654 MMC_REG_STATUS); |
612 mxcmci_finish_data(host, datastat); 613 614 if (host->req->stop) { 615 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 616 mxcmci_finish_request(host, host->req); 617 return; 618 } 619 } else { --- 61 unchanged lines hidden (view full) --- 681 682static irqreturn_t mxcmci_irq(int irq, void *devid) 683{ 684 struct mxcmci_host *host = devid; 685 unsigned long flags; 686 bool sdio_irq; 687 u32 stat; 688 | 655 mxcmci_finish_data(host, datastat); 656 657 if (host->req->stop) { 658 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 659 mxcmci_finish_request(host, host->req); 660 return; 661 } 662 } else { --- 61 unchanged lines hidden (view full) --- 724 725static irqreturn_t mxcmci_irq(int irq, void *devid) 726{ 727 struct mxcmci_host *host = devid; 728 unsigned long flags; 729 bool sdio_irq; 730 u32 stat; 731 |
689 stat = readl(host->base + MMC_REG_STATUS); 690 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 691 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS); | 732 stat = mxcmci_readl(host, MMC_REG_STATUS); 733 mxcmci_writel(host, 734 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 735 STATUS_WRITE_OP_DONE), 736 MMC_REG_STATUS); |
692 693 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 694 695 spin_lock_irqsave(&host->lock, flags); 696 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 697 spin_unlock_irqrestore(&host->lock, flags); 698 699 if (mxcmci_use_dma(host) && 700 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE))) | 737 738 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 739 740 spin_lock_irqsave(&host->lock, flags); 741 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 742 spin_unlock_irqrestore(&host->lock, flags); 743 744 if (mxcmci_use_dma(host) && 745 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE))) |
701 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 702 host->base + MMC_REG_STATUS); | 746 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 747 MMC_REG_STATUS); |
703 704 if (sdio_irq) { | 748 749 if (sdio_irq) { |
705 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS); | 750 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS); |
706 mmc_signal_sdio_irq(host->mmc); 707 } 708 709 if (stat & STATUS_END_CMD_RESP) 710 mxcmci_cmd_done(host, stat); 711 712 if (mxcmci_use_dma(host) && 713 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) { --- 65 unchanged lines hidden (view full) --- 779 break; 780 781 if (prescaler == 0) 782 prescaler = 1; 783 else 784 prescaler <<= 1; 785 } 786 | 751 mmc_signal_sdio_irq(host->mmc); 752 } 753 754 if (stat & STATUS_END_CMD_RESP) 755 mxcmci_cmd_done(host, stat); 756 757 if (mxcmci_use_dma(host) && 758 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) { --- 65 unchanged lines hidden (view full) --- 824 break; 825 826 if (prescaler == 0) 827 prescaler = 1; 828 else 829 prescaler <<= 1; 830 } 831 |
787 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE); | 832 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE); |
788 789 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 790 prescaler, divider, clk_in, clk_ios); 791} 792 793static int mxcmci_setup_dma(struct mmc_host *mmc) 794{ 795 struct mxcmci_host *host = mmc_priv(mmc); --- 46 unchanged lines hidden (view full) --- 842 host->power_mode = ios->power_mode; 843 844 if (ios->power_mode == MMC_POWER_ON) 845 host->cmdat |= CMD_DAT_CONT_INIT; 846 } 847 848 if (ios->clock) { 849 mxcmci_set_clk_rate(host, ios->clock); | 833 834 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 835 prescaler, divider, clk_in, clk_ios); 836} 837 838static int mxcmci_setup_dma(struct mmc_host *mmc) 839{ 840 struct mxcmci_host *host = mmc_priv(mmc); --- 46 unchanged lines hidden (view full) --- 887 host->power_mode = ios->power_mode; 888 889 if (ios->power_mode == MMC_POWER_ON) 890 host->cmdat |= CMD_DAT_CONT_INIT; 891 } 892 893 if (ios->clock) { 894 mxcmci_set_clk_rate(host, ios->clock); |
850 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); | 895 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); |
851 } else { | 896 } else { |
852 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); | 897 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK); |
853 } 854 855 host->clock = ios->clock; 856} 857 858static irqreturn_t mxcmci_detect_irq(int irq, void *data) 859{ 860 struct mmc_host *mmc = data; --- 20 unchanged lines hidden (view full) --- 881static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 882{ 883 struct mxcmci_host *host = mmc_priv(mmc); 884 unsigned long flags; 885 u32 int_cntr; 886 887 spin_lock_irqsave(&host->lock, flags); 888 host->use_sdio = enable; | 898 } 899 900 host->clock = ios->clock; 901} 902 903static irqreturn_t mxcmci_detect_irq(int irq, void *data) 904{ 905 struct mmc_host *mmc = data; --- 20 unchanged lines hidden (view full) --- 926static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 927{ 928 struct mxcmci_host *host = mmc_priv(mmc); 929 unsigned long flags; 930 u32 int_cntr; 931 932 spin_lock_irqsave(&host->lock, flags); 933 host->use_sdio = enable; |
889 int_cntr = readl(host->base + MMC_REG_INT_CNTR); | 934 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR); |
890 891 if (enable) 892 int_cntr |= INT_SDIO_IRQ_EN; 893 else 894 int_cntr &= ~INT_SDIO_IRQ_EN; 895 | 935 936 if (enable) 937 int_cntr |= INT_SDIO_IRQ_EN; 938 else 939 int_cntr &= ~INT_SDIO_IRQ_EN; 940 |
896 writel(int_cntr, host->base + MMC_REG_INT_CNTR); | 941 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); |
897 spin_unlock_irqrestore(&host->lock, flags); 898} 899 900static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 901{ 902 struct mxcmci_host *mxcmci = mmc_priv(host); 903 904 /* --- 21 unchanged lines hidden (view full) --- 926 return true; 927} 928 929static void mxcmci_watchdog(unsigned long data) 930{ 931 struct mmc_host *mmc = (struct mmc_host *)data; 932 struct mxcmci_host *host = mmc_priv(mmc); 933 struct mmc_request *req = host->req; | 942 spin_unlock_irqrestore(&host->lock, flags); 943} 944 945static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 946{ 947 struct mxcmci_host *mxcmci = mmc_priv(host); 948 949 /* --- 21 unchanged lines hidden (view full) --- 971 return true; 972} 973 974static void mxcmci_watchdog(unsigned long data) 975{ 976 struct mmc_host *mmc = (struct mmc_host *)data; 977 struct mxcmci_host *host = mmc_priv(mmc); 978 struct mmc_request *req = host->req; |
934 unsigned int stat = readl(host->base + MMC_REG_STATUS); | 979 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS); |
935 936 if (host->dma_dir == DMA_FROM_DEVICE) { 937 dmaengine_terminate_all(host->dma); 938 dev_err(mmc_dev(host->mmc), 939 "%s: read time out (status = 0x%08x)\n", 940 __func__, stat); 941 } else { 942 dev_err(mmc_dev(host->mmc), --- 26 unchanged lines hidden (view full) --- 969 struct mxcmci_host *host = NULL; 970 struct resource *iores, *r; 971 int ret = 0, irq; 972 bool dat3_card_detect = false; 973 dma_cap_mask_t mask; 974 const struct of_device_id *of_id; 975 struct imxmmc_platform_data *pdata = pdev->dev.platform_data; 976 | 980 981 if (host->dma_dir == DMA_FROM_DEVICE) { 982 dmaengine_terminate_all(host->dma); 983 dev_err(mmc_dev(host->mmc), 984 "%s: read time out (status = 0x%08x)\n", 985 __func__, stat); 986 } else { 987 dev_err(mmc_dev(host->mmc), --- 26 unchanged lines hidden (view full) --- 1014 struct mxcmci_host *host = NULL; 1015 struct resource *iores, *r; 1016 int ret = 0, irq; 1017 bool dat3_card_detect = false; 1018 dma_cap_mask_t mask; 1019 const struct of_device_id *of_id; 1020 struct imxmmc_platform_data *pdata = pdev->dev.platform_data; 1021 |
977 pr_info("i.MX SDHC driver\n"); | 1022 pr_info("i.MX/MPC512x SDHC driver\n"); |
978 979 of_id = of_match_device(mxcmci_of_match, &pdev->dev); 980 981 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 982 irq = platform_get_irq(pdev, 0); 983 if (!iores || irq < 0) 984 return -EINVAL; 985 --- 69 unchanged lines hidden (view full) --- 1055 goto out_iounmap; 1056 } 1057 1058 clk_prepare_enable(host->clk_per); 1059 clk_prepare_enable(host->clk_ipg); 1060 1061 mxcmci_softreset(host); 1062 | 1023 1024 of_id = of_match_device(mxcmci_of_match, &pdev->dev); 1025 1026 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1027 irq = platform_get_irq(pdev, 0); 1028 if (!iores || irq < 0) 1029 return -EINVAL; 1030 --- 69 unchanged lines hidden (view full) --- 1100 goto out_iounmap; 1101 } 1102 1103 clk_prepare_enable(host->clk_per); 1104 clk_prepare_enable(host->clk_ipg); 1105 1106 mxcmci_softreset(host); 1107 |
1063 host->rev_no = readw(host->base + MMC_REG_REV_NO); | 1108 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO); |
1064 if (host->rev_no != 0x400) { 1065 ret = -ENODEV; 1066 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1067 host->rev_no); 1068 goto out_clk_put; 1069 } 1070 1071 mmc->f_min = clk_get_rate(host->clk_per) >> 16; 1072 mmc->f_max = clk_get_rate(host->clk_per) >> 1; 1073 1074 /* recommended in data sheet */ | 1109 if (host->rev_no != 0x400) { 1110 ret = -ENODEV; 1111 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1112 host->rev_no); 1113 goto out_clk_put; 1114 } 1115 1116 mmc->f_min = clk_get_rate(host->clk_per) >> 16; 1117 mmc->f_max = clk_get_rate(host->clk_per) >> 1; 1118 1119 /* recommended in data sheet */ |
1075 writew(0x2db4, host->base + MMC_REG_READ_TO); | 1120 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO); |
1076 | 1121 |
1077 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR); | 1122 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR); |
1078 1079 if (!host->pdata) { 1080 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx"); 1081 } else { 1082 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1083 if (r) { 1084 host->dmareq = r->start; 1085 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; --- 139 unchanged lines hidden --- | 1123 1124 if (!host->pdata) { 1125 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx"); 1126 } else { 1127 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1128 if (r) { 1129 host->dmareq = r->start; 1130 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; --- 139 unchanged lines hidden --- |