mmci.c (00e930d87d196ae70e225eee88957441c10ff872) mmci.c (46b723dd867d599420fb640c0eaf2a866ef721d4)
1/*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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47#define DRIVER_NAME "mmci-pl18x"
48
49#ifdef CONFIG_DMA_ENGINE
50void mmci_variant_init(struct mmci_host *host);
51#else
52static inline void mmci_variant_init(struct mmci_host *host) {}
53#endif
54
1/*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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47#define DRIVER_NAME "mmci-pl18x"
48
49#ifdef CONFIG_DMA_ENGINE
50void mmci_variant_init(struct mmci_host *host);
51#else
52static inline void mmci_variant_init(struct mmci_host *host) {}
53#endif
54
55#ifdef CONFIG_MMC_STM32_SDMMC
56void sdmmc_variant_init(struct mmci_host *host);
57#else
58static inline void sdmmc_variant_init(struct mmci_host *host) {}
59#endif
60
55static unsigned int fmax = 515633;
56
57static struct variant_data variant_arm = {
58 .fifosize = 16 * 4,
59 .fifohalfsize = 8 * 4,
60 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
61 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
62 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,

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254 .st_clkdiv = true,
255 .pwrreg_powerup = MCI_PWR_ON,
256 .f_max = 48000000,
257 .pwrreg_clkgate = true,
258 .pwrreg_nopower = true,
259 .init = mmci_variant_init,
260};
261
61static unsigned int fmax = 515633;
62
63static struct variant_data variant_arm = {
64 .fifosize = 16 * 4,
65 .fifohalfsize = 8 * 4,
66 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
67 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
68 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,

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260 .st_clkdiv = true,
261 .pwrreg_powerup = MCI_PWR_ON,
262 .f_max = 48000000,
263 .pwrreg_clkgate = true,
264 .pwrreg_nopower = true,
265 .init = mmci_variant_init,
266};
267
268static struct variant_data variant_stm32_sdmmc = {
269 .fifosize = 16 * 4,
270 .fifohalfsize = 8 * 4,
271 .f_max = 208000000,
272 .stm32_clkdiv = true,
273 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
274 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
275 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
276 .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
277 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
278 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
279 .datactrl_first = true,
280 .datacnt_useless = true,
281 .datalength_bits = 25,
282 .datactrl_blocksz = 14,
283 .stm32_idmabsize_mask = GENMASK(12, 5),
284 .init = sdmmc_variant_init,
285};
286
262static struct variant_data variant_qcom = {
263 .fifosize = 16 * 4,
264 .fifohalfsize = 8 * 4,
265 .clkreg = MCI_CLK_ENABLE,
266 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
267 MCI_QCOM_CLK_SELECT_IN_FBCLK,
268 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
269 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,

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1731 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1732 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1733 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1734 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1735 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1736 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1737 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1738 host->pwr_reg_add |= MCI_ST_FBCLKEN;
287static struct variant_data variant_qcom = {
288 .fifosize = 16 * 4,
289 .fifohalfsize = 8 * 4,
290 .clkreg = MCI_CLK_ENABLE,
291 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
292 MCI_QCOM_CLK_SELECT_IN_FBCLK,
293 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
294 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,

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1756 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1757 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1758 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1759 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1760 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1761 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1762 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1763 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1764 if (of_get_property(np, "st,sig-dir", NULL))
1765 host->pwr_reg_add |= MCI_STM32_DIRPOL;
1766 if (of_get_property(np, "st,neg-edge", NULL))
1767 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
1768 if (of_get_property(np, "st,use-ckin", NULL))
1769 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
1739
1740 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1741 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1742 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1743 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1744
1745 return 0;
1746}

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2172 .mask = 0xf0ffffff,
2173 .data = &variant_ux500v2,
2174 },
2175 {
2176 .id = 0x00880180,
2177 .mask = 0x00ffffff,
2178 .data = &variant_stm32,
2179 },
1770
1771 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1772 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1773 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1774 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1775
1776 return 0;
1777}

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2203 .mask = 0xf0ffffff,
2204 .data = &variant_ux500v2,
2205 },
2206 {
2207 .id = 0x00880180,
2208 .mask = 0x00ffffff,
2209 .data = &variant_stm32,
2210 },
2211 {
2212 .id = 0x10153180,
2213 .mask = 0xf0ffffff,
2214 .data = &variant_stm32_sdmmc,
2215 },
2180 /* Qualcomm variants */
2181 {
2182 .id = 0x00051180,
2183 .mask = 0x000fffff,
2184 .data = &variant_qcom,
2185 },
2186 { 0, 0 },
2187};

--- 19 unchanged lines hidden --- 		2216 /* Qualcomm variants */
2217 {
2218 .id = 0x00051180,
2219 .mask = 0x000fffff,
2220 .data = &variant_qcom,
2221 },
2222 { 0, 0 },
2223};

--- 19 unchanged lines hidden ---