| dw_mmc.h (01b653c2199b55ea798f9b4e224d055317524d8f) | dw_mmc.h (e382ab741252471383e9990583258e3054f66963) |
|---|---|
| 1/* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify --- 300 unchanged lines hidden (view full) --- 309#define SDMMC_PLDMND 0x084 310#define SDMMC_DBADDR 0x088 311#define SDMMC_IDSTS 0x08c 312#define SDMMC_IDINTEN 0x090 313#define SDMMC_DSCADDR 0x094 314#define SDMMC_BUFADDR 0x098 315#define SDMMC_CDTHRCTL 0x100 316#define SDMMC_UHS_REG_EXT 0x108 | 1/* 2 * Synopsys DesignWare Multimedia Card Interface driver 3 * (Based on NXP driver for lpc 31xx) 4 * 5 * Copyright (C) 2009 NXP Semiconductors 6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 7 * 8 * This program is free software; you can redistribute it and/or modify --- 300 unchanged lines hidden (view full) --- 309#define SDMMC_PLDMND 0x084 310#define SDMMC_DBADDR 0x088 311#define SDMMC_IDSTS 0x08c 312#define SDMMC_IDINTEN 0x090 313#define SDMMC_DSCADDR 0x094 314#define SDMMC_BUFADDR 0x098 315#define SDMMC_CDTHRCTL 0x100 316#define SDMMC_UHS_REG_EXT 0x108 |
| 317#define SDMMC_DDR_REG 0x10c |
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| 317#define SDMMC_ENABLE_SHIFT 0x110 318#define SDMMC_DATA(x) (x) 319/* 320 * Registers to support idmac 64-bit address mode 321 */ 322#define SDMMC_DBADDRL 0x088 323#define SDMMC_DBADDRU 0x08c 324#define SDMMC_IDSTS64 0x090 --- 109 unchanged lines hidden (view full) --- 434#define SDMMC_RST_HWACTIVE 0x1 435/* Version ID register define */ 436#define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 437/* Card read threshold */ 438#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 439#define SDMMC_CARD_WR_THR_EN BIT(2) 440#define SDMMC_CARD_RD_THR_EN BIT(0) 441/* UHS-1 register defines */ | 318#define SDMMC_ENABLE_SHIFT 0x110 319#define SDMMC_DATA(x) (x) 320/* 321 * Registers to support idmac 64-bit address mode 322 */ 323#define SDMMC_DBADDRL 0x088 324#define SDMMC_DBADDRU 0x08c 325#define SDMMC_IDSTS64 0x090 --- 109 unchanged lines hidden (view full) --- 435#define SDMMC_RST_HWACTIVE 0x1 436/* Version ID register define */ 437#define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 438/* Card read threshold */ 439#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 440#define SDMMC_CARD_WR_THR_EN BIT(2) 441#define SDMMC_CARD_RD_THR_EN BIT(0) 442/* UHS-1 register defines */ |
| 443#define SDMMC_UHS_DDR BIT(16) |
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| 442#define SDMMC_UHS_18V BIT(0) | 444#define SDMMC_UHS_18V BIT(0) |
| 445/* DDR register defines */ 446#define SDMMC_DDR_HS400 BIT(31) 447/* Enable shift register defines */ 448#define SDMMC_ENABLE_PHASE BIT(0) |
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| 443/* All ctrl reset bits */ 444#define SDMMC_CTRL_ALL_RESET_FLAGS \ 445 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 446 447/* FIFO register access macros. These should not change the data endian-ness 448 * as they are written to memory to be dealt with by the upper layers 449 */ 450#define mci_fifo_readw(__reg) __raw_readw(__reg) --- 115 unchanged lines hidden --- | 449/* All ctrl reset bits */ 450#define SDMMC_CTRL_ALL_RESET_FLAGS \ 451 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 452 453/* FIFO register access macros. These should not change the data endian-ness 454 * as they are written to memory to be dealt with by the upper layers 455 */ 456#define mci_fifo_readw(__reg) __raw_readw(__reg) --- 115 unchanged lines hidden --- |