atmel-mci.c (d4e0045c4ed300781d2d4cbab57d05ed5e665a37) atmel-mci.c (ef4b160f280f81cab477ba733177c3a658e60a1c)
1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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39#include <linux/pm_runtime.h>
40#include <linux/pinctrl/consumer.h>
41
42#include <asm/cacheflush.h>
43#include <asm/io.h>
44#include <asm/unaligned.h>
45
46/*
1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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39#include <linux/pm_runtime.h>
40#include <linux/pinctrl/consumer.h>
41
42#include <asm/cacheflush.h>
43#include <asm/io.h>
44#include <asm/unaligned.h>
45
46/*
47 * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
47 * Superset of MCI IP registers integrated in Atmel AT91 Processor
48 * Registers and bitfields marked with [2] are only available in MCI2
49 */
50
51/* MCI Register Definitions */
52#define ATMCI_CR 0x0000 /* Control */
53#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
54#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
55#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */

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167#define ATMCI_REGS_SIZE 0x100
168
169/* Register access macros */
170#define atmci_readl(port, reg) \
171 __raw_readl((port)->regs + reg)
172#define atmci_writel(port, reg, value) \
173 __raw_writel((value), (port)->regs + reg)
174
48 * Registers and bitfields marked with [2] are only available in MCI2
49 */
50
51/* MCI Register Definitions */
52#define ATMCI_CR 0x0000 /* Control */
53#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
54#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
55#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */

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167#define ATMCI_REGS_SIZE 0x100
168
169/* Register access macros */
170#define atmci_readl(port, reg) \
171 __raw_readl((port)->regs + reg)
172#define atmci_writel(port, reg, value) \
173 __raw_writel((value), (port)->regs + reg)
174
175/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
176#ifdef CONFIG_AVR32
177# define ATMCI_PDC_CONNECTED 0
178#else
179# define ATMCI_PDC_CONNECTED 1
180#endif
181
182#define AUTOSUSPEND_DELAY 50
183
184#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
185#define ATMCI_DMA_THRESHOLD 16
186
187enum {
188 EVENT_CMD_RDY = 0,
189 EVENT_XFER_COMPLETE,

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1544 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1545 break;
1546 case MMC_POWER_UP:
1547 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1548 if (!IS_ERR(mmc->supply.vmmc))
1549 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1550 break;
1551 default:
175#define AUTOSUSPEND_DELAY 50
176
177#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
178#define ATMCI_DMA_THRESHOLD 16
179
180enum {
181 EVENT_CMD_RDY = 0,
182 EVENT_XFER_COMPLETE,

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1537 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1538 break;
1539 case MMC_POWER_UP:
1540 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1541 if (!IS_ERR(mmc->supply.vmmc))
1542 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1543 break;
1544 default:
1552 /*
1553 * TODO: None of the currently available AVR32-based
1554 * boards allow MMC power to be turned off. Implement
1555 * power control when this can be tested properly.
1556 *
1557 * We also need to hook this into the clock management
1558 * somehow so that newly inserted cards aren't
1559 * subjected to a fast clock before we have a chance
1560 * to figure out what the maximum rate is. Currently,
1561 * there's no way to avoid this, and there never will
1562 * be for boards that don't support power control.
1563 */
1564 break;
1565 }
1545 break;
1546 }
1566
1567}
1568
1569static int atmci_get_ro(struct mmc_host *mmc)
1570{
1571 int read_only = -ENOSYS;
1572 struct atmel_mci_slot *slot = mmc_priv(mmc);
1573
1574 if (gpio_is_valid(slot->wp_pin)) {

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2459{
2460 unsigned int version;
2461
2462 version = atmci_get_version(host);
2463 dev_info(&host->pdev->dev,
2464 "version: 0x%x\n", version);
2465
2466 host->caps.has_dma_conf_reg = 0;
1547}
1548
1549static int atmci_get_ro(struct mmc_host *mmc)
1550{
1551 int read_only = -ENOSYS;
1552 struct atmel_mci_slot *slot = mmc_priv(mmc);
1553
1554 if (gpio_is_valid(slot->wp_pin)) {

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2439{
2440 unsigned int version;
2441
2442 version = atmci_get_version(host);
2443 dev_info(&host->pdev->dev,
2444 "version: 0x%x\n", version);
2445
2446 host->caps.has_dma_conf_reg = 0;
2467 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2447 host->caps.has_pdc = 1;
2468 host->caps.has_cfg_reg = 0;
2469 host->caps.has_cstor_reg = 0;
2470 host->caps.has_highspeed = 0;
2471 host->caps.has_rwproof = 0;
2472 host->caps.has_odd_clk_div = 0;
2473 host->caps.has_bad_data_ordering = 1;
2474 host->caps.need_reset_after_xfer = 1;
2475 host->caps.need_blksz_mul_4 = 1;

--- 262 unchanged lines hidden --- 		2448 host->caps.has_cfg_reg = 0;
2449 host->caps.has_cstor_reg = 0;
2450 host->caps.has_highspeed = 0;
2451 host->caps.has_rwproof = 0;
2452 host->caps.has_odd_clk_div = 0;
2453 host->caps.has_bad_data_ordering = 1;
2454 host->caps.need_reset_after_xfer = 1;
2455 host->caps.need_blksz_mul_4 = 1;

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