grufile.c (9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) grufile.c (cf8e8658100d4eae80ce9b21f7a81cb024dd5057)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * SN Platform GRU Driver
4 *
5 * FILE OPERATIONS & DRIVER INITIALIZATION
6 *
7 * This file supports the user system call for file open, close, mmap, etc.
8 * This also incudes the driver initialization code.

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332 } else {
333 BUG();
334 }
335
336 *corep = core;
337 return mmr;
338}
339
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * SN Platform GRU Driver
4 *
5 * FILE OPERATIONS & DRIVER INITIALIZATION
6 *
7 * This file supports the user system call for file open, close, mmap, etc.
8 * This also incudes the driver initialization code.

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332 } else {
333 BUG();
334 }
335
336 *corep = core;
337 return mmr;
338}
339
340#ifdef CONFIG_IA64
341
342static int gru_irq_count[GRU_CHIPLETS_PER_BLADE];
343
344static void gru_noop(struct irq_data *d)
345{
346}
347
348static struct irq_chip gru_chip[GRU_CHIPLETS_PER_BLADE] = {
349 [0 ... GRU_CHIPLETS_PER_BLADE - 1] {
350 .irq_mask = gru_noop,
351 .irq_unmask = gru_noop,
352 .irq_ack = gru_noop
353 }
354};
355
356static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
357 irq_handler_t irq_handler, int cpu, int blade)
358{
359 unsigned long mmr;
340static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
341 irq_handler_t irq_handler, int cpu, int blade)
342{
343 unsigned long mmr;
360 int irq = IRQ_GRU + chiplet;
361 int ret, core;
362
363 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
364 if (mmr == 0)
365 return 0;
366
367 if (gru_irq_count[chiplet] == 0) {
368 gru_chip[chiplet].name = irq_name;
369 ret = irq_set_chip(irq, &gru_chip[chiplet]);
370 if (ret) {
371 printk(KERN_ERR "%s: set_irq_chip failed, errno=%d\n",
372 GRU_DRIVER_ID_STR, -ret);
373 return ret;
374 }
375
376 ret = request_irq(irq, irq_handler, 0, irq_name, NULL);
377 if (ret) {
378 printk(KERN_ERR "%s: request_irq failed, errno=%d\n",
379 GRU_DRIVER_ID_STR, -ret);
380 return ret;
381 }
382 }
383 gru_irq_count[chiplet]++;
384
385 return 0;
386}
387
388static void gru_chiplet_teardown_tlb_irq(int chiplet, int cpu, int blade)
389{
390 unsigned long mmr;
391 int core, irq = IRQ_GRU + chiplet;
392
393 if (gru_irq_count[chiplet] == 0)
394 return;
395
396 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
397 if (mmr == 0)
398 return;
399
400 if (--gru_irq_count[chiplet] == 0)
401 free_irq(irq, NULL);
402}
403
404#elif defined CONFIG_X86_64
405
406static int gru_chiplet_setup_tlb_irq(int chiplet, char *irq_name,
407 irq_handler_t irq_handler, int cpu, int blade)
408{
409 unsigned long mmr;
410 int irq, core;
411 int ret;
412
413 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
414 if (mmr == 0)
415 return 0;
416
417 irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);

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442 irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
443 if (irq) {
444 free_irq(irq, NULL);
445 uv_teardown_irq(irq);
446 }
447 }
448}
449
344 int irq, core;
345 int ret;
346
347 mmr = gru_chiplet_cpu_to_mmr(chiplet, cpu, &core);
348 if (mmr == 0)
349 return 0;
350
351 irq = uv_setup_irq(irq_name, cpu, blade, mmr, UV_AFFINITY_CPU);

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376 irq = gru_base[blade]->bs_grus[chiplet].gs_irq[core];
377 if (irq) {
378 free_irq(irq, NULL);
379 uv_teardown_irq(irq);
380 }
381 }
382}
383
450#endif
451
452static void gru_teardown_tlb_irqs(void)
453{
454 int blade;
455 int cpu;
456
457 for_each_online_cpu(cpu) {
458 blade = uv_cpu_to_blade_id(cpu);
459 gru_chiplet_teardown_tlb_irq(0, cpu, blade);

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509 */
510static int __init gru_init(void)
511{
512 int ret;
513
514 if (!gru_supported())
515 return 0;
516
384static void gru_teardown_tlb_irqs(void)
385{
386 int blade;
387 int cpu;
388
389 for_each_online_cpu(cpu) {
390 blade = uv_cpu_to_blade_id(cpu);
391 gru_chiplet_teardown_tlb_irq(0, cpu, blade);

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441 */
442static int __init gru_init(void)
443{
444 int ret;
445
446 if (!gru_supported())
447 return 0;
448
517#if defined CONFIG_IA64
518 gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
519#else
520 gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG) &
521 0x7fffffffffffUL;
449 gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG) &
450 0x7fffffffffffUL;
522#endif
523 gru_start_vaddr = __va(gru_start_paddr);
524 gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
525 printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
526 gru_start_paddr, gru_end_paddr);
527 ret = misc_register(&gru_miscdev);
528 if (ret) {
529 printk(KERN_ERR "%s: misc_register failed\n",
530 GRU_DRIVER_ID_STR);

--- 82 unchanged lines hidden --- 		451 gru_start_vaddr = __va(gru_start_paddr);
452 gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
453 printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
454 gru_start_paddr, gru_end_paddr);
455 ret = misc_register(&gru_miscdev);
456 if (ret) {
457 printk(KERN_ERR "%s: misc_register failed\n",
458 GRU_DRIVER_ID_STR);

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