native.c (cbffa3a5146a90f46806cef3a98b8be5833727e8) native.c (4752876c71701b7663a5ded789058ab2c05f7d0f)
1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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962 return 0;
963}
964
965int cxl_check_error(struct cxl_afu *afu)
966{
967 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
968}
969
1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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962 return 0;
963}
964
965int cxl_check_error(struct cxl_afu *afu)
966{
967 return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL);
968}
969
970static bool native_support_attributes(const char *attr_name,
971 enum cxl_attrs type)
972{
973 return true;
974}
975
970static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
971{
972 if (unlikely(!cxl_ops->link_ok(afu->adapter)))
973 return -EIO;
974 if (unlikely(off >= afu->crs_len))
975 return -ERANGE;
976 *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
977 (cr * afu->crs_len) + off);

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1021 .alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
1022 .release_irq_ranges = cxl_pci_release_irq_ranges,
1023 .setup_irq = cxl_pci_setup_irq,
1024 .handle_psl_slice_error = native_handle_psl_slice_error,
1025 .psl_interrupt = NULL,
1026 .ack_irq = native_ack_irq,
1027 .attach_process = native_attach_process,
1028 .detach_process = native_detach_process,
976static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out)
977{
978 if (unlikely(!cxl_ops->link_ok(afu->adapter)))
979 return -EIO;
980 if (unlikely(off >= afu->crs_len))
981 return -ERANGE;
982 *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset +
983 (cr * afu->crs_len) + off);

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1027 .alloc_irq_ranges = cxl_pci_alloc_irq_ranges,
1028 .release_irq_ranges = cxl_pci_release_irq_ranges,
1029 .setup_irq = cxl_pci_setup_irq,
1030 .handle_psl_slice_error = native_handle_psl_slice_error,
1031 .psl_interrupt = NULL,
1032 .ack_irq = native_ack_irq,
1033 .attach_process = native_attach_process,
1034 .detach_process = native_detach_process,
1035 .support_attributes = native_support_attributes,
1029 .link_ok = cxl_adapter_link_ok,
1030 .release_afu = cxl_pci_release_afu,
1031 .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
1032 .afu_check_and_enable = native_afu_check_and_enable,
1033 .afu_activate_mode = native_afu_activate_mode,
1034 .afu_deactivate_mode = native_afu_deactivate_mode,
1035 .afu_reset = native_afu_reset,
1036 .afu_cr_read8 = native_afu_cr_read8,
1037 .afu_cr_read16 = native_afu_cr_read16,
1038 .afu_cr_read32 = native_afu_cr_read32,
1039 .afu_cr_read64 = native_afu_cr_read64,
1040};
1036 .link_ok = cxl_adapter_link_ok,
1037 .release_afu = cxl_pci_release_afu,
1038 .afu_read_err_buffer = cxl_pci_afu_read_err_buffer,
1039 .afu_check_and_enable = native_afu_check_and_enable,
1040 .afu_activate_mode = native_afu_activate_mode,
1041 .afu_deactivate_mode = native_afu_deactivate_mode,
1042 .afu_reset = native_afu_reset,
1043 .afu_cr_read8 = native_afu_cr_read8,
1044 .afu_cr_read16 = native_afu_cr_read16,
1045 .afu_cr_read32 = native_afu_cr_read32,
1046 .afu_cr_read64 = native_afu_cr_read64,
1047};