native.c (218ea31039e84901b449c3769035456688f6e17d) native.c (3ced8d73006321bd2a0412fa0ff4b065a02e7514)
1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

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581}
582
583#ifdef CONFIG_CPU_LITTLE_ENDIAN
584#define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
585#else
586#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
587#endif
588
1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */

--- 572 unchanged lines hidden (view full) ---

581}
582
583#ifdef CONFIG_CPU_LITTLE_ENDIAN
584#define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE)
585#else
586#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
587#endif
588
589static u64 calculate_sr(struct cxl_context *ctx)
589u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9)
590{
591 u64 sr = 0;
592
593 set_endian(sr);
590{
591 u64 sr = 0;
592
593 set_endian(sr);
594 if (ctx->master)
594 if (master)
595 sr |= CXL_PSL_SR_An_MP;
596 if (mfspr(SPRN_LPCR) & LPCR_TC)
597 sr |= CXL_PSL_SR_An_TC;
595 sr |= CXL_PSL_SR_An_MP;
596 if (mfspr(SPRN_LPCR) & LPCR_TC)
597 sr |= CXL_PSL_SR_An_TC;
598 if (ctx->kernel) {
599 if (!ctx->real_mode)
598 if (kernel) {
599 if (!real_mode)
600 sr |= CXL_PSL_SR_An_R;
601 sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
602 } else {
603 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
604 if (radix_enabled())
605 sr |= CXL_PSL_SR_An_HV;
606 else
607 sr &= ~(CXL_PSL_SR_An_HV);
608 if (!test_tsk_thread_flag(current, TIF_32BIT))
609 sr |= CXL_PSL_SR_An_SF;
610 }
600 sr |= CXL_PSL_SR_An_R;
601 sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
602 } else {
603 sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
604 if (radix_enabled())
605 sr |= CXL_PSL_SR_An_HV;
606 else
607 sr &= ~(CXL_PSL_SR_An_HV);
608 if (!test_tsk_thread_flag(current, TIF_32BIT))
609 sr |= CXL_PSL_SR_An_SF;
610 }
611 if (cxl_is_power9()) {
611 if (p9) {
612 if (radix_enabled())
613 sr |= CXL_PSL_SR_An_XLAT_ror;
614 else
615 sr |= CXL_PSL_SR_An_XLAT_hpt;
616 }
617 return sr;
618}
619
612 if (radix_enabled())
613 sr |= CXL_PSL_SR_An_XLAT_ror;
614 else
615 sr |= CXL_PSL_SR_An_XLAT_hpt;
616 }
617 return sr;
618}
619
620static u64 calculate_sr(struct cxl_context *ctx)
621{
622 return cxl_calculate_sr(ctx->master, ctx->kernel, ctx->real_mode,
623 cxl_is_power9());
624}
625
620static void update_ivtes_directed(struct cxl_context *ctx)
621{
622 bool need_update = (ctx->status == STARTED);
623 int r;
624
625 if (need_update) {
626 WARN_ON(terminate_process_element(ctx));
627 WARN_ON(remove_process_element(ctx));

--- 931 unchanged lines hidden --- 		626static void update_ivtes_directed(struct cxl_context *ctx)
627{
628 bool need_update = (ctx->status == STARTED);
629 int r;
630
631 if (need_update) {
632 WARN_ON(terminate_process_element(ctx));
633 WARN_ON(remove_process_element(ctx));

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