rtsx_pcr.c (81148a7ab79e8a5f1e9379d5fcdd7fb73896ec18) rtsx_pcr.c (849a9366cba92cb5dc9dc1161ef49416a290aae9)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */

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18#include <linux/platform_device.h>
19#include <linux/mfd/core.h>
20#include <linux/rtsx_pci.h>
21#include <linux/mmc/card.h>
22#include <asm/unaligned.h>
23
24#include "rtsx_pcr.h"
25#include "rts5261.h"
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */

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18#include <linux/platform_device.h>
19#include <linux/mfd/core.h>
20#include <linux/rtsx_pci.h>
21#include <linux/mmc/card.h>
22#include <asm/unaligned.h>
23
24#include "rtsx_pcr.h"
25#include "rts5261.h"
26#include "rts5228.h"
26
27static bool msi_en = true;
28module_param(msi_en, bool, S_IRUGO | S_IWUSR);
29MODULE_PARM_DESC(msi_en, "Enable MSI");
30
31static DEFINE_IDR(rtsx_pci_idr);
32static DEFINE_SPINLOCK(rtsx_pci_lock);
33

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45 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
46 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
47 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
48 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
49 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
50 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
51 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
52 { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
27
28static bool msi_en = true;
29module_param(msi_en, bool, S_IRUGO | S_IWUSR);
30MODULE_PARM_DESC(msi_en, "Enable MSI");
31
32static DEFINE_IDR(rtsx_pci_idr);
33static DEFINE_SPINLOCK(rtsx_pci_lock);
34

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46 { PCI_DEVICE(0x10EC, 0x522A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
47 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
48 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
49 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
50 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
51 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
52 { PCI_DEVICE(0x10EC, 0x5260), PCI_CLASS_OTHERS << 16, 0xFF0000 },
53 { PCI_DEVICE(0x10EC, 0x5261), PCI_CLASS_OTHERS << 16, 0xFF0000 },
54 { PCI_DEVICE(0x10EC, 0x5228), PCI_CLASS_OTHERS << 16, 0xFF0000 },
53 { 0, }
54};
55
56MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
57
58static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
59{
60 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,

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201}
202EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
203
204int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
205{
206 int err, i, finished = 0;
207 u8 tmp;
208
55 { 0, }
56};
57
58MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
59
60static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
61{
62 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,

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203}
204EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
205
206int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
207{
208 int err, i, finished = 0;
209 u8 tmp;
210
209 rtsx_pci_init_cmd(pcr);
211 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
212 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
213 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
214 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
210
215
211 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
212 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
213 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
214 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
215
216 err = rtsx_pci_send_cmd(pcr, 100);
217 if (err < 0)
218 return err;
219
220 for (i = 0; i < 100000; i++) {
221 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
222 if (err < 0)
223 return err;
224
225 if (!(tmp & 0x80)) {
226 finished = 1;
227 break;

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242 return __rtsx_pci_write_phy_register(pcr, addr, val);
243}
244EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
245
246int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
247{
248 int err, i, finished = 0;
249 u16 data;
216 for (i = 0; i < 100000; i++) {
217 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
218 if (err < 0)
219 return err;
220
221 if (!(tmp & 0x80)) {
222 finished = 1;
223 break;

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238 return __rtsx_pci_write_phy_register(pcr, addr, val);
239}
240EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
241
242int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
243{
244 int err, i, finished = 0;
245 u16 data;
250 u8 *ptr, tmp;
246 u8 tmp, val1, val2;
251
247
252 rtsx_pci_init_cmd(pcr);
248 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
249 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
253
250
254 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
255 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
256
257 err = rtsx_pci_send_cmd(pcr, 100);
258 if (err < 0)
259 return err;
260
261 for (i = 0; i < 100000; i++) {
262 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
263 if (err < 0)
264 return err;
265
266 if (!(tmp & 0x80)) {
267 finished = 1;
268 break;
269 }
270 }
271
272 if (!finished)
273 return -ETIMEDOUT;
274
251 for (i = 0; i < 100000; i++) {
252 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
253 if (err < 0)
254 return err;
255
256 if (!(tmp & 0x80)) {
257 finished = 1;
258 break;
259 }
260 }
261
262 if (!finished)
263 return -ETIMEDOUT;
264
275 rtsx_pci_init_cmd(pcr);
265 rtsx_pci_read_register(pcr, PHYDATA0, &val1);
266 rtsx_pci_read_register(pcr, PHYDATA1, &val2);
267 data = val1 | (val2 << 8);
276
268
277 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
278 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
279
280 err = rtsx_pci_send_cmd(pcr, 100);
281 if (err < 0)
282 return err;
283
284 ptr = rtsx_pci_get_cmd_data(pcr);
285 data = ((u16)ptr[1] << 8) | ptr[0];
286
287 if (val)
288 *val = data;
289
290 return 0;
291}
292
293int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
294{

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412 u64 val;
413 u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
414
415 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
416
417 if (end)
418 option |= RTSX_SG_END;
419
269 if (val)
270 *val = data;
271
272 return 0;
273}
274
275int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
276{

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394 u64 val;
395 u8 option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA;
396
397 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
398
399 if (end)
400 option |= RTSX_SG_END;
401
420 if (PCI_PID(pcr) == PID_5261) {
402 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
421 if (len > 0xFFFF)
422 val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
423 | (((u64)len >> 16) << 6) | option;
424 else
425 val = ((u64)addr << 32) | ((u64)len << 16) | option;
426 } else {
427 val = ((u64)addr << 32) | ((u64)len << 12) | option;
428 }

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718 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
719 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
720 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
721 };
722
723 if (PCI_PID(pcr) == PID_5261)
724 return rts5261_pci_switch_clock(pcr, card_clock,
725 ssc_depth, initial_mode, double_clk, vpclk);
403 if (len > 0xFFFF)
404 val = ((u64)addr << 32) | (((u64)len & 0xFFFF) << 16)
405 | (((u64)len >> 16) << 6) | option;
406 else
407 val = ((u64)addr << 32) | ((u64)len << 16) | option;
408 } else {
409 val = ((u64)addr << 32) | ((u64)len << 12) | option;
410 }

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700 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
701 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
702 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
703 };
704
705 if (PCI_PID(pcr) == PID_5261)
706 return rts5261_pci_switch_clock(pcr, card_clock,
707 ssc_depth, initial_mode, double_clk, vpclk);
708 if (PCI_PID(pcr) == PID_5228)
709 return rts5228_pci_switch_clock(pcr, card_clock,
710 ssc_depth, initial_mode, double_clk, vpclk);
726
727 if (initial_mode) {
728 /* We use 250k(around) here, in initial stage */
729 clk_divider = SD_CLK_DIVIDE_128;
730 card_clock = 30000000;
731 } else {
732 clk_divider = SD_CLK_DIVIDE_0;
733 }

--- 463 unchanged lines hidden (view full) ---

1197 u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1198
1199 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1200 udelay(100);
1201 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1202 }
1203}
1204
711
712 if (initial_mode) {
713 /* We use 250k(around) here, in initial stage */
714 clk_divider = SD_CLK_DIVIDE_128;
715 card_clock = 30000000;
716 } else {
717 clk_divider = SD_CLK_DIVIDE_0;
718 }

--- 463 unchanged lines hidden (view full) ---

1182 u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1183
1184 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1185 udelay(100);
1186 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1187 }
1188}
1189
1190void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1191{
1192 u16 val;
1193
1194 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1195 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1196 val |= 1<<9;
1197 rtsx_pci_write_phy_register(pcr, 0x01, val);
1198 }
1199 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1200 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1201 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1202 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1203
1204}
1205
1206void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1207{
1208 u16 val;
1209
1210 if ((PCI_PID(pcr) != PID_525A) && (PCI_PID(pcr) != PID_5260)) {
1211 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1212 val &= ~(1<<9);
1213 rtsx_pci_write_phy_register(pcr, 0x01, val);
1214 }
1215 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1216 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1217
1218}
1219
1205int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1206{
1207 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1208 MS_CLK_EN | SD40_CLK_EN, 0);
1209 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1210 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1211
1212 msleep(50);

--- 15 unchanged lines hidden (view full) ---

1228
1229 return 0;
1230}
1231
1232static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1233{
1234 int err;
1235
1220int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1221{
1222 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1223 MS_CLK_EN | SD40_CLK_EN, 0);
1224 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1225 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1226
1227 msleep(50);

--- 15 unchanged lines hidden (view full) ---

1243
1244 return 0;
1245}
1246
1247static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1248{
1249 int err;
1250
1251 if (PCI_PID(pcr) == PID_5228)
1252 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1253 RTS5228_LDO1_SR_0_5);
1254
1236 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
1237 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1238
1239 rtsx_pci_enable_bus_int(pcr);
1240
1241 /* Power on SSC */
1242 if (PCI_PID(pcr) == PID_5261) {
1243 /* Gating real mcu clock */

--- 31 unchanged lines hidden (view full) ---

1275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1276 0xFF, pcr->card_drive_sel);
1277 /* Enable SSC Clock */
1278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1279 0xFF, SSC_8X_EN | SSC_SEL_4M);
1280 if (PCI_PID(pcr) == PID_5261)
1281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1282 RTS5261_SSC_DEPTH_2M);
1255 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
1256 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1257
1258 rtsx_pci_enable_bus_int(pcr);
1259
1260 /* Power on SSC */
1261 if (PCI_PID(pcr) == PID_5261) {
1262 /* Gating real mcu clock */

--- 31 unchanged lines hidden (view full) ---

1294 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1295 0xFF, pcr->card_drive_sel);
1296 /* Enable SSC Clock */
1297 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1298 0xFF, SSC_8X_EN | SSC_SEL_4M);
1299 if (PCI_PID(pcr) == PID_5261)
1300 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1301 RTS5261_SSC_DEPTH_2M);
1302 else if (PCI_PID(pcr) == PID_5228)
1303 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1304 RTS5228_SSC_DEPTH_2M);
1283 else
1284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1285
1286 /* Disable cd_pwr_save */
1287 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1288 /* Clear Link Ready Interrupt */
1289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1290 LINK_RDY_INT, LINK_RDY_INT);

--- 18 unchanged lines hidden (view full) ---

1309 return err;
1310
1311 switch (PCI_PID(pcr)) {
1312 case PID_5250:
1313 case PID_524A:
1314 case PID_525A:
1315 case PID_5260:
1316 case PID_5261:
1305 else
1306 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1307
1308 /* Disable cd_pwr_save */
1309 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1310 /* Clear Link Ready Interrupt */
1311 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1312 LINK_RDY_INT, LINK_RDY_INT);

--- 18 unchanged lines hidden (view full) ---

1331 return err;
1332
1333 switch (PCI_PID(pcr)) {
1334 case PID_5250:
1335 case PID_524A:
1336 case PID_525A:
1337 case PID_5260:
1338 case PID_5261:
1339 case PID_5228:
1317 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1318 break;
1319 default:
1320 break;
1321 }
1322
1323 /*init ocp*/
1324 rtsx_pci_init_ocp(pcr);

--- 71 unchanged lines hidden (view full) ---

1396
1397 case 0x5260:
1398 rts5260_init_params(pcr);
1399 break;
1400
1401 case 0x5261:
1402 rts5261_init_params(pcr);
1403 break;
1340 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1341 break;
1342 default:
1343 break;
1344 }
1345
1346 /*init ocp*/
1347 rtsx_pci_init_ocp(pcr);

--- 71 unchanged lines hidden (view full) ---

1419
1420 case 0x5260:
1421 rts5260_init_params(pcr);
1422 break;
1423
1424 case 0x5261:
1425 rts5261_init_params(pcr);
1426 break;
1427
1428 case 0x5228:
1429 rts5228_init_params(pcr);
1430 break;
1404 }
1405
1406 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1407 PCI_PID(pcr), pcr->ic_version);
1408
1409 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1410 GFP_KERNEL);
1411 if (!pcr->slots)

--- 297 unchanged lines hidden --- 		1431 }
1432
1433 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1434 PCI_PID(pcr), pcr->ic_version);
1435
1436 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1437 GFP_KERNEL);
1438 if (!pcr->slots)

--- 297 unchanged lines hidden ---