rtsx_pcr.c (3eb66e91a25497065c5322b1268cbc3953642227) rtsx_pcr.c (bede03a579b3b4a036003c4862cc1baa4ddc351f)
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.

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698
699
700 return rtsx_pci_set_pull_ctl(pcr, tbl);
701}
702EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
703
704static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
705{
1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.

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698
699
700 return rtsx_pci_set_pull_ctl(pcr, tbl);
701}
702EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
703
704static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
705{
706 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
706 struct rtsx_hw_param *hw_param = &pcr->hw_param;
707
707
708 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
709 | hw_param->interrupt_en;
710
708 if (pcr->num_slots > 1)
709 pcr->bier |= MS_INT_EN;
710
711 /* Enable Bus Interrupt */
712 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
713
714 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
715}

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964 pcr->slots[RTSX_SD_CARD].p_dev);
965 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
966 pcr->slots[RTSX_MS_CARD].card_event(
967 pcr->slots[RTSX_MS_CARD].p_dev);
968}
969
970static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
971{
711 if (pcr->num_slots > 1)
712 pcr->bier |= MS_INT_EN;
713
714 /* Enable Bus Interrupt */
715 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
716
717 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
718}

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967 pcr->slots[RTSX_SD_CARD].p_dev);
968 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
969 pcr->slots[RTSX_MS_CARD].card_event(
970 pcr->slots[RTSX_MS_CARD].p_dev);
971}
972
973static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
974{
972 if (pcr->ops->process_ocp)
975 if (pcr->ops->process_ocp) {
973 pcr->ops->process_ocp(pcr);
976 pcr->ops->process_ocp(pcr);
977 } else {
978 if (!pcr->option.ocp_en)
979 return;
980 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
981 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
982 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
983 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
984 rtsx_pci_clear_ocpstat(pcr);
985 pcr->ocp_stat = 0;
986 }
987 }
974}
975
976static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
977{
978 if (pcr->option.ocp_en)
979 rtsx_pci_process_ocp(pcr);
980
981 return 0;

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1034 complete(pcr->done);
1035 } else if (int_reg & TRANS_OK_INT) {
1036 pcr->trans_result = TRANS_RESULT_OK;
1037 if (pcr->done)
1038 complete(pcr->done);
1039 }
1040 }
1041
988}
989
990static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
991{
992 if (pcr->option.ocp_en)
993 rtsx_pci_process_ocp(pcr);
994
995 return 0;

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1048 complete(pcr->done);
1049 } else if (int_reg & TRANS_OK_INT) {
1050 pcr->trans_result = TRANS_RESULT_OK;
1051 if (pcr->done)
1052 complete(pcr->done);
1053 }
1054 }
1055
1042 if (pcr->card_inserted || pcr->card_removed)
1056 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
1043 schedule_delayed_work(&pcr->carddet_work,
1044 msecs_to_jiffies(200));
1045
1046 spin_unlock(&pcr->lock);
1047 return IRQ_HANDLED;
1048}
1049
1050static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)

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1139 pcr->ops->force_power_down(pcr, pm_state);
1140}
1141#endif
1142
1143void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1144{
1145 u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
1146
1057 schedule_delayed_work(&pcr->carddet_work,
1058 msecs_to_jiffies(200));
1059
1060 spin_unlock(&pcr->lock);
1061 return IRQ_HANDLED;
1062}
1063
1064static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)

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1153 pcr->ops->force_power_down(pcr, pm_state);
1154}
1155#endif
1156
1157void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1158{
1159 u8 val = SD_OCP_INT_EN | SD_DETECT_EN;
1160
1147 if (pcr->ops->enable_ocp)
1161 if (pcr->ops->enable_ocp) {
1148 pcr->ops->enable_ocp(pcr);
1162 pcr->ops->enable_ocp(pcr);
1149 else
1163 } else {
1164 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1150 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1165 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1166 }
1151
1152}
1153
1154void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1155{
1156 u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
1157
1167
1168}
1169
1170void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1171{
1172 u8 mask = SD_OCP_INT_EN | SD_DETECT_EN;
1173
1158 if (pcr->ops->disable_ocp)
1174 if (pcr->ops->disable_ocp) {
1159 pcr->ops->disable_ocp(pcr);
1175 pcr->ops->disable_ocp(pcr);
1160 else
1176 } else {
1161 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1177 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1178 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1179 OC_POWER_DOWN);
1180 }
1162}
1163
1164void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1165{
1166 if (pcr->ops->init_ocp) {
1167 pcr->ops->init_ocp(pcr);
1168 } else {
1169 struct rtsx_cr_option *option = &(pcr->option);
1170
1171 if (option->ocp_en) {
1181}
1182
1183void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1184{
1185 if (pcr->ops->init_ocp) {
1186 pcr->ops->init_ocp(pcr);
1187 } else {
1188 struct rtsx_cr_option *option = &(pcr->option);
1189
1190 if (option->ocp_en) {
1172 u8 val = option->sd_400mA_ocp_thd;
1191 u8 val = option->sd_800mA_ocp_thd;
1173
1174 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1175 rtsx_pci_write_register(pcr, REG_OCPPARA1,
1176 SD_OCP_TIME_MASK, SD_OCP_TIME_800);
1177 rtsx_pci_write_register(pcr, REG_OCPPARA2,
1178 SD_OCP_THD_MASK, val);
1179 rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1180 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);

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1199{
1200 if (pcr->ops->clear_ocpstat) {
1201 pcr->ops->clear_ocpstat(pcr);
1202 } else {
1203 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
1204 u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1205
1206 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1192
1193 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1194 rtsx_pci_write_register(pcr, REG_OCPPARA1,
1195 SD_OCP_TIME_MASK, SD_OCP_TIME_800);
1196 rtsx_pci_write_register(pcr, REG_OCPPARA2,
1197 SD_OCP_THD_MASK, val);
1198 rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1199 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);

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1218{
1219 if (pcr->ops->clear_ocpstat) {
1220 pcr->ops->clear_ocpstat(pcr);
1221 } else {
1222 u8 mask = SD_OCP_INT_CLR | SD_OC_CLR;
1223 u8 val = SD_OCP_INT_CLR | SD_OC_CLR;
1224
1225 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1226 udelay(100);
1207 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1208 }
1209}
1210
1211int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1212{
1213 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1214 MS_CLK_EN | SD40_CLK_EN, 0);
1215 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1227 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1228 }
1229}
1230
1231int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1232{
1233 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1234 MS_CLK_EN | SD40_CLK_EN, 0);
1235 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1216
1217 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1218
1219 msleep(50);
1220
1221 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1222
1223 return 0;
1224}

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1308 case PID_525A:
1309 case PID_5260:
1310 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1311 break;
1312 default:
1313 break;
1314 }
1315
1236 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1237
1238 msleep(50);
1239
1240 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1241
1242 return 0;
1243}

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1327 case PID_525A:
1328 case PID_5260:
1329 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1330 break;
1331 default:
1332 break;
1333 }
1334
1335 /*init ocp*/
1336 rtsx_pci_init_ocp(pcr);
1337
1316 /* Enable clk_request_n to enable clock power management */
1317 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
1318 /* Enter L1 when host tx idle */
1319 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1320
1321 if (pcr->ops->extra_init_hw) {
1322 err = pcr->ops->extra_init_hw(pcr);
1323 if (err < 0)

--- 370 unchanged lines hidden --- 		1338 /* Enable clk_request_n to enable clock power management */
1339 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
1340 /* Enter L1 when host tx idle */
1341 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1342
1343 if (pcr->ops->extra_init_hw) {
1344 err = pcr->ops->extra_init_hw(pcr);
1345 if (err < 0)

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