rts5261.c (98817a84ff1c755c347ac633ff017a623a631fad) rts5261.c (22bf3251d7b7da0339f41ec27f2c3d4e0ec02255)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Rui FENG <rui_feng@realsil.com.cn>
8 * Wei WANG <wei_wang@realsil.com.cn>

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54 0xFF, driving[drive_sel][1]);
55
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
57 0xFF, driving[drive_sel][2]);
58}
59
60static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
61{
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Rui FENG <rui_feng@realsil.com.cn>
8 * Wei WANG <wei_wang@realsil.com.cn>

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54 0xFF, driving[drive_sel][1]);
55
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
57 0xFF, driving[drive_sel][2]);
58}
59
60static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
61{
62 struct pci_dev *pdev = pcr->pci;
62 u32 reg;
63 u32 reg;
64
63 /* 0x814~0x817 */
65 /* 0x814~0x817 */
64 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
66 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
65 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
66
67 if (!rts5261_vendor_setting_valid(reg)) {
68 pcr_dbg(pcr, "skip fetch vendor setting\n");
69 return;
70 }
71
72 pcr->card_drive_sel &= 0x3F;
73 pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg);
74
75 if (rts5261_reg_check_reverse_socket(reg))
76 pcr->flags |= PCR_REVERSE_SOCKET;
77
78 /* 0x724~0x727 */
67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
68
69 if (!rts5261_vendor_setting_valid(reg)) {
70 pcr_dbg(pcr, "skip fetch vendor setting\n");
71 return;
72 }
73
74 pcr->card_drive_sel &= 0x3F;
75 pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg);
76
77 if (rts5261_reg_check_reverse_socket(reg))
78 pcr->flags |= PCR_REVERSE_SOCKET;
79
80 /* 0x724~0x727 */
79 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
81 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
80 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
81
82 pcr->aspm_en = rts5261_reg_to_aspm(reg);
83 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
84 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
85}
86
87static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)

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356 rts5261_clear_ocpstat(pcr);
357 pcr->ocp_stat = 0;
358 }
359
360}
361
362static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
363{
82 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
83
84 pcr->aspm_en = rts5261_reg_to_aspm(reg);
85 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
86 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
87}
88
89static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)

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358 rts5261_clear_ocpstat(pcr);
359 pcr->ocp_stat = 0;
360 }
361
362}
363
364static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
365{
366 struct pci_dev *pdev = pcr->pci;
364 int retval;
365 u32 lval, i;
366 u8 valid, efuse_valid, tmp;
367
368 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
369 REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
370 REG_EFUSE_POR | REG_EFUSE_POWERON);
371 udelay(1);

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381 if ((tmp & 0x80) == 0)
382 break;
383 }
384 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
385 efuse_valid = ((tmp & 0x0C) >> 2);
386 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
387
388 if (efuse_valid == 0) {
367 int retval;
368 u32 lval, i;
369 u8 valid, efuse_valid, tmp;
370
371 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
372 REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
373 REG_EFUSE_POR | REG_EFUSE_POWERON);
374 udelay(1);

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384 if ((tmp & 0x80) == 0)
385 break;
386 }
387 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
388 efuse_valid = ((tmp & 0x0C) >> 2);
389 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
390
391 if (efuse_valid == 0) {
389 retval = rtsx_pci_read_config_dword(pcr,
390 PCR_SETTING_REG2, &lval);
392 retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
391 if (retval != 0)
392 pcr_dbg(pcr, "read 0x814 DW fail\n");
393 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
394 /* 0x816 */
395 valid = (u8)((lval >> 16) & 0x03);
396 pcr_dbg(pcr, "0x816: %d\n", valid);
397 }
398 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
399 REG_EFUSE_POR, 0);
400 pcr_dbg(pcr, "Disable efuse por!\n");
401
393 if (retval != 0)
394 pcr_dbg(pcr, "read 0x814 DW fail\n");
395 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
396 /* 0x816 */
397 valid = (u8)((lval >> 16) & 0x03);
398 pcr_dbg(pcr, "0x816: %d\n", valid);
399 }
400 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
401 REG_EFUSE_POR, 0);
402 pcr_dbg(pcr, "Disable efuse por!\n");
403
402 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &lval);
404 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
403 lval = lval & 0x00FFFFFF;
405 lval = lval & 0x00FFFFFF;
404 retval = rtsx_pci_write_config_dword(pcr, PCR_SETTING_REG2, lval);
406 retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval);
405 if (retval != 0)
406 pcr_dbg(pcr, "write config fail\n");
407
408 return retval;
409}
410
411static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
412{
407 if (retval != 0)
408 pcr_dbg(pcr, "write config fail\n");
409
410 return retval;
411}
412
413static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
414{
415 struct pci_dev *pdev = pcr->pci;
413 u32 lval;
414 struct rtsx_cr_option *option = &pcr->option;
415
416 u32 lval;
417 struct rtsx_cr_option *option = &pcr->option;
418
416 rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_REG1, &lval);
419 pci_read_config_dword(pdev, PCR_ASPM_SETTING_REG1, &lval);
417
418 if (lval & ASPM_L1_1_EN_MASK)
419 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
420 else
421 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
422
423 if (lval & ASPM_L1_2_EN_MASK)
424 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);

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434 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
435 else
436 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
437
438 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
439 if (option->ltr_en) {
440 u16 val;
441
420
421 if (lval & ASPM_L1_1_EN_MASK)
422 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
423 else
424 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
425
426 if (lval & ASPM_L1_2_EN_MASK)
427 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);

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437 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
438 else
439 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
440
441 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
442 if (option->ltr_en) {
443 u16 val;
444
442 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
445 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
443 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
444 option->ltr_enabled = true;
445 option->ltr_active = true;
446 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
447 } else {
448 option->ltr_enabled = false;
449 }
450 }

--- 318 unchanged lines hidden --- 		446 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
447 option->ltr_enabled = true;
448 option->ltr_active = true;
449 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
450 } else {
451 option->ltr_enabled = false;
452 }
453 }

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