rts5260.c (98817a84ff1c755c347ac633ff017a623a631fad) rts5260.c (22bf3251d7b7da0339f41ec27f2c3d4e0ec02255)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Steven FENG <steven_feng@realsil.com.cn>
8 * Rui FENG <rui_feng@realsil.com.cn>

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59 0xFF, driving[drive_sel][1]);
60
61 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
62 0xFF, driving[drive_sel][2]);
63}
64
65static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
66{
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Steven FENG <steven_feng@realsil.com.cn>
8 * Rui FENG <rui_feng@realsil.com.cn>

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59 0xFF, driving[drive_sel][1]);
60
61 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
62 0xFF, driving[drive_sel][2]);
63}
64
65static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
66{
67 struct pci_dev *pdev = pcr->pci;
67 u32 reg;
68
68 u32 reg;
69
69 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
70 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
70 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
71
72 if (!rtsx_vendor_setting_valid(reg)) {
73 pcr_dbg(pcr, "skip fetch vendor setting\n");
74 return;
75 }
76
77 pcr->aspm_en = rtsx_reg_to_aspm(reg);
78 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
79 pcr->card_drive_sel &= 0x3F;
80 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
81
71 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
72
73 if (!rtsx_vendor_setting_valid(reg)) {
74 pcr_dbg(pcr, "skip fetch vendor setting\n");
75 return;
76 }
77
78 pcr->aspm_en = rtsx_reg_to_aspm(reg);
79 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
80 pcr->card_drive_sel &= 0x3F;
81 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
82
82 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
83 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
83 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
84 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
85 if (rtsx_reg_check_reverse_socket(reg))
86 pcr->flags |= PCR_REVERSE_SOCKET;
87}
88
89static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
90{

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491 0xFF, CFG_LP_FPWM_VALUE_DEFAULT);
492 /*No Power Saving WA*/
493 rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
494 0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);
495}
496
497static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
498{
84 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
85 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
86 if (rtsx_reg_check_reverse_socket(reg))
87 pcr->flags |= PCR_REVERSE_SOCKET;
88}
89
90static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
91{

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492 0xFF, CFG_LP_FPWM_VALUE_DEFAULT);
493 /*No Power Saving WA*/
494 rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
495 0xFF, CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT);
496}
497
498static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
499{
500 struct pci_dev *pdev = pcr->pci;
499 struct rtsx_cr_option *option = &pcr->option;
500 u32 lval;
501
501 struct rtsx_cr_option *option = &pcr->option;
502 u32 lval;
503
502 rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_5260, &lval);
504 pci_read_config_dword(pdev, PCR_ASPM_SETTING_5260, &lval);
503
504 if (lval & ASPM_L1_1_EN_MASK)
505 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
506
507 if (lval & ASPM_L1_2_EN_MASK)
508 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
509
510 if (lval & PM_L1_1_EN_MASK)
511 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
512
513 if (lval & PM_L1_2_EN_MASK)
514 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
515
516 rts5260_pwr_saving_setting(pcr);
517
518 if (option->ltr_en) {
519 u16 val;
520
505
506 if (lval & ASPM_L1_1_EN_MASK)
507 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
508
509 if (lval & ASPM_L1_2_EN_MASK)
510 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
511
512 if (lval & PM_L1_1_EN_MASK)
513 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
514
515 if (lval & PM_L1_2_EN_MASK)
516 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
517
518 rts5260_pwr_saving_setting(pcr);
519
520 if (option->ltr_en) {
521 u16 val;
522
521 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
523 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
522 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
523 option->ltr_enabled = true;
524 option->ltr_active = true;
525 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
526 } else {
527 option->ltr_enabled = false;
528 }
529 }

--- 143 unchanged lines hidden --- 		524 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
525 option->ltr_enabled = true;
526 option->ltr_active = true;
527 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
528 } else {
529 option->ltr_enabled = false;
530 }
531 }

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