rts5260.c (0268eed10f12f785a618880920d90ee306fb2a50) rts5260.c (7c33e3c4c79ac5def79e7c773e38a7113eb14204)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Steven FENG <steven_feng@realsil.com.cn>
8 * Rui FENG <rui_feng@realsil.com.cn>

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21 u8 val;
22
23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 return val & IC_VERSION_MASK;
25}
26
27static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
28{
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2016-2017 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Steven FENG <steven_feng@realsil.com.cn>
8 * Rui FENG <rui_feng@realsil.com.cn>

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21 u8 val;
22
23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 return val & IC_VERSION_MASK;
25}
26
27static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
28{
29 u8 driving_3v3[6][3] = {
30 {0x94, 0x94, 0x94},
31 {0x11, 0x11, 0x18},
32 {0x55, 0x55, 0x5C},
33 {0x94, 0x94, 0x94},
34 {0x94, 0x94, 0x94},
35 {0xFF, 0xFF, 0xFF},
29 u8 driving_3v3[4][3] = {
30 {0x11, 0x11, 0x11},
31 {0x22, 0x22, 0x22},
32 {0x55, 0x55, 0x55},
33 {0x33, 0x33, 0x33},
36 };
34 };
37 u8 driving_1v8[6][3] = {
38 {0x9A, 0x89, 0x89},
39 {0xC4, 0xC4, 0xC4},
40 {0x3C, 0x3C, 0x3C},
35 u8 driving_1v8[4][3] = {
36 {0x35, 0x33, 0x33},
37 {0x8A, 0x88, 0x88},
38 {0xBD, 0xBB, 0xBB},
41 {0x9B, 0x99, 0x99},
39 {0x9B, 0x99, 0x99},
42 {0x9A, 0x89, 0x89},
43 {0xFE, 0xFE, 0xFE},
44 };
45 u8 (*driving)[3], drive_sel;
46
47 if (voltage == OUTPUT_3V3) {
48 driving = driving_3v3;
49 drive_sel = pcr->sd30_drive_sel_3v3;
50 } else {
51 driving = driving_1v8;
52 drive_sel = pcr->sd30_drive_sel_1v8;
53 }
54
55 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
56 0xFF, driving[drive_sel][0]);
57
58 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
59 0xFF, driving[drive_sel][1]);
60
40 };
41 u8 (*driving)[3], drive_sel;
42
43 if (voltage == OUTPUT_3V3) {
44 driving = driving_3v3;
45 drive_sel = pcr->sd30_drive_sel_3v3;
46 } else {
47 driving = driving_1v8;
48 drive_sel = pcr->sd30_drive_sel_1v8;
49 }
50
51 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
52 0xFF, driving[drive_sel][0]);
53
54 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
55 0xFF, driving[drive_sel][1]);
56
61 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
57 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
62 0xFF, driving[drive_sel][2]);
63}
64
65static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
66{
67 struct pci_dev *pdev = pcr->pci;
68 u32 reg;
69

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77
78 pcr->aspm_en = rtsx_reg_to_aspm(reg);
79 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
80 pcr->card_drive_sel &= 0x3F;
81 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
82
83 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
84 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
58 0xFF, driving[drive_sel][2]);
59}
60
61static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
62{
63 struct pci_dev *pdev = pcr->pci;
64 u32 reg;
65

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73
74 pcr->aspm_en = rtsx_reg_to_aspm(reg);
75 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
76 pcr->card_drive_sel &= 0x3F;
77 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
78
79 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
80 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
81 if (rtsx_check_mmc_support(reg))
82 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
85 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
86 if (rtsx_reg_check_reverse_socket(reg))
87 pcr->flags |= PCR_REVERSE_SOCKET;
88}
89
90static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
91{
92 return rtsx_pci_write_register(pcr, OLT_LED_CTL,

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554 */
555 if (option->force_clkreq_0)
556 rtsx_pci_write_register(pcr, PETXCFG,
557 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
558 else
559 rtsx_pci_write_register(pcr, PETXCFG,
560 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
561
83 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
84 if (rtsx_reg_check_reverse_socket(reg))
85 pcr->flags |= PCR_REVERSE_SOCKET;
86}
87
88static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
89{
90 return rtsx_pci_write_register(pcr, OLT_LED_CTL,

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552 */
553 if (option->force_clkreq_0)
554 rtsx_pci_write_register(pcr, PETXCFG,
555 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
556 else
557 rtsx_pci_write_register(pcr, PETXCFG,
558 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
559
560 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
561
562 return 0;
563}
564
565static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
566{
567 struct rtsx_cr_option *option = &pcr->option;
568 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
569 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);

--- 94 unchanged lines hidden --- 		562 return 0;
563}
564
565static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
566{
567 struct rtsx_cr_option *option = &pcr->option;
568 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
569 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST);

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