rts5249.c (98817a84ff1c755c347ac633ff017a623a631fad) rts5249.c (22bf3251d7b7da0339f41ec27f2c3d4e0ec02255)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */

--- 41 unchanged lines hidden (view full) ---

50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
51 0xFF, driving[drive_sel][1]);
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
53 0xFF, driving[drive_sel][2]);
54}
55
56static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
57{
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 */

--- 41 unchanged lines hidden (view full) ---

50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
51 0xFF, driving[drive_sel][1]);
52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
53 0xFF, driving[drive_sel][2]);
54}
55
56static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
57{
58 struct pci_dev *pdev = pcr->pci;
58 u32 reg;
59
59 u32 reg;
60
60 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
61 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
61 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
62
63 if (!rtsx_vendor_setting_valid(reg)) {
64 pcr_dbg(pcr, "skip fetch vendor setting\n");
65 return;
66 }
67
68 pcr->aspm_en = rtsx_reg_to_aspm(reg);
69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
70 pcr->card_drive_sel &= 0x3F;
71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
72
62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
63
64 if (!rtsx_vendor_setting_valid(reg)) {
65 pcr_dbg(pcr, "skip fetch vendor setting\n");
66 return;
67 }
68
69 pcr->aspm_en = rtsx_reg_to_aspm(reg);
70 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
71 pcr->card_drive_sel &= 0x3F;
72 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
73
73 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
74 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
75 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
76 if (rtsx_reg_check_reverse_socket(reg))
77 pcr->flags |= PCR_REVERSE_SOCKET;
78}
79
80static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
81{

--- 6 unchanged lines hidden (view full) ---

88 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
89 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
90
91 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
92}
93
94static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
95{
75 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
76 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
77 if (rtsx_reg_check_reverse_socket(reg))
78 pcr->flags |= PCR_REVERSE_SOCKET;
79}
80
81static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
82{

--- 6 unchanged lines hidden (view full) ---

89 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
90 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
91
92 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
93}
94
95static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
96{
97 struct pci_dev *pdev = pcr->pci;
96 struct rtsx_cr_option *option = &(pcr->option);
97 u32 lval;
98
99 if (CHK_PCI_PID(pcr, PID_524A))
98 struct rtsx_cr_option *option = &(pcr->option);
99 u32 lval;
100
101 if (CHK_PCI_PID(pcr, PID_524A))
100 rtsx_pci_read_config_dword(pcr,
102 pci_read_config_dword(pdev,
101 PCR_ASPM_SETTING_REG1, &lval);
102 else
103 PCR_ASPM_SETTING_REG1, &lval);
104 else
103 rtsx_pci_read_config_dword(pcr,
105 pci_read_config_dword(pdev,
104 PCR_ASPM_SETTING_REG2, &lval);
105
106 if (lval & ASPM_L1_1_EN_MASK)
107 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
108
109 if (lval & ASPM_L1_2_EN_MASK)
110 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
111
112 if (lval & PM_L1_1_EN_MASK)
113 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
114
115 if (lval & PM_L1_2_EN_MASK)
116 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
117
118 if (option->ltr_en) {
119 u16 val;
120
106 PCR_ASPM_SETTING_REG2, &lval);
107
108 if (lval & ASPM_L1_1_EN_MASK)
109 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
110
111 if (lval & ASPM_L1_2_EN_MASK)
112 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
113
114 if (lval & PM_L1_1_EN_MASK)
115 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
116
117 if (lval & PM_L1_2_EN_MASK)
118 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
119
120 if (option->ltr_en) {
121 u16 val;
122
121 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
123 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
122 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
123 option->ltr_enabled = true;
124 option->ltr_active = true;
125 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
126 } else {
127 option->ltr_enabled = false;
128 }
129 }

--- 592 unchanged lines hidden --- 		124 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
125 option->ltr_enabled = true;
126 option->ltr_active = true;
127 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
128 } else {
129 option->ltr_enabled = false;
130 }
131 }

--- 592 unchanged lines hidden ---