rc5t583-irq.c (0588000eac9ba4178cebade437da3b28e8fad48f) rc5t583-irq.c (3f9be35bd9090eaa2f68ed9b24efdbf3abcf4b28)
1/*
2 * Interrupt driver for RICOH583 power management chip.
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * based on code
8 * Copyright (C) 2011 RICOH COMPANY,LTD

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340 if (!irq_base) {
341 dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");
342 return -EINVAL;
343 }
344
345 mutex_init(&rc5t583->irq_lock);
346
347 /* Initailize all int register to 0 */
1/*
2 * Interrupt driver for RICOH583 power management chip.
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * based on code
8 * Copyright (C) 2011 RICOH COMPANY,LTD

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340 if (!irq_base) {
341 dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");
342 return -EINVAL;
343 }
344
345 mutex_init(&rc5t583->irq_lock);
346
347 /* Initailize all int register to 0 */
348 for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) {
348 for (i = 0; i < RC5T583_MAX_INTERRUPT_EN_REGS; i++) {
349 ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
350 rc5t583->irq_en_reg[i]);
351 if (ret < 0)
352 dev_warn(rc5t583->dev,
353 "Error in writing reg 0x%02x error: %d\n",
354 irq_en_add[i], ret);
355 }
356

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349 ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
350 rc5t583->irq_en_reg[i]);
351 if (ret < 0)
352 dev_warn(rc5t583->dev,
353 "Error in writing reg 0x%02x error: %d\n",
354 irq_en_add[i], ret);
355 }
356

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