max14577.c (eccb80cc22354a12255c2579247a92a30a4c881b) max14577.c (c7846852ec8f304c629963202fa565452e8fe34c)
1/*
2 * max14577.c - mfd core driver for the Maxim 14577
3 *
4 * Copyright (C) 2013 Samsung Electrnoics
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 * Krzysztof Kozlowski <k.kozlowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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61 .reg_bits = 8,
62 .val_bits = 8,
63 .volatile_reg = max14577_muic_volatile_reg,
64 .max_register = MAX14577_REG_END,
65};
66
67static const struct regmap_irq max14577_irqs[] = {
68 /* INT1 interrupts */
1/*
2 * max14577.c - mfd core driver for the Maxim 14577
3 *
4 * Copyright (C) 2013 Samsung Electrnoics
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 * Krzysztof Kozlowski <k.kozlowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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61 .reg_bits = 8,
62 .val_bits = 8,
63 .volatile_reg = max14577_muic_volatile_reg,
64 .max_register = MAX14577_REG_END,
65};
66
67static const struct regmap_irq max14577_irqs[] = {
68 /* INT1 interrupts */
69 { .reg_offset = 0, .mask = INT1_ADC_MASK, },
70 { .reg_offset = 0, .mask = INT1_ADCLOW_MASK, },
71 { .reg_offset = 0, .mask = INT1_ADCERR_MASK, },
69 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
70 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
71 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
72 /* INT2 interrupts */
72 /* INT2 interrupts */
73 { .reg_offset = 1, .mask = INT2_CHGTYP_MASK, },
74 { .reg_offset = 1, .mask = INT2_CHGDETRUN_MASK, },
75 { .reg_offset = 1, .mask = INT2_DCDTMR_MASK, },
76 { .reg_offset = 1, .mask = INT2_DBCHG_MASK, },
77 { .reg_offset = 1, .mask = INT2_VBVOLT_MASK, },
73 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
74 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
75 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
76 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
77 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
78 /* INT3 interrupts */
78 /* INT3 interrupts */
79 { .reg_offset = 2, .mask = INT3_EOC_MASK, },
80 { .reg_offset = 2, .mask = INT3_CGMBC_MASK, },
81 { .reg_offset = 2, .mask = INT3_OVP_MASK, },
82 { .reg_offset = 2, .mask = INT3_MBCCHGERR_MASK, },
79 { .reg_offset = 2, .mask = MAX14577_INT3_EOC_MASK, },
80 { .reg_offset = 2, .mask = MAX14577_INT3_CGMBC_MASK, },
81 { .reg_offset = 2, .mask = MAX14577_INT3_OVP_MASK, },
82 { .reg_offset = 2, .mask = MAX14577_INT3_MBCCHGERR_MASK, },
83};
84
85static const struct regmap_irq_chip max14577_irq_chip = {
86 .name = "max14577",
87 .status_base = MAX14577_REG_INT1,
88 .mask_base = MAX14577_REG_INTMASK1,
89 .mask_invert = 1,
90 .num_regs = 3,

--- 188 unchanged lines hidden --- 		83};
84
85static const struct regmap_irq_chip max14577_irq_chip = {
86 .name = "max14577",
87 .status_base = MAX14577_REG_INT1,
88 .mask_base = MAX14577_REG_INTMASK1,
89 .mask_invert = 1,
90 .num_regs = 3,

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