max14577.c (aee2a57c7482c712052b877218aa2c5bc0fe8626) max14577.c (4706a5253bcc502a5889feb98392ea7b15dd936e)
1/*
2 * max14577.c - mfd core driver for the Maxim 14577/77836
3 *
4 * Copyright (C) 2014 Samsung Electrnoics
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 * Krzysztof Kozlowski <k.kozlowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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142 .num_irqs = ARRAY_SIZE(max14577_irqs),
143};
144
145static const struct regmap_irq max77836_muic_irqs[] = {
146 /* INT1 interrupts */
147 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
148 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
149 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
1/*
2 * max14577.c - mfd core driver for the Maxim 14577/77836
3 *
4 * Copyright (C) 2014 Samsung Electrnoics
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 * Krzysztof Kozlowski <k.kozlowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify

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142 .num_irqs = ARRAY_SIZE(max14577_irqs),
143};
144
145static const struct regmap_irq max77836_muic_irqs[] = {
146 /* INT1 interrupts */
147 { .reg_offset = 0, .mask = MAX14577_INT1_ADC_MASK, },
148 { .reg_offset = 0, .mask = MAX14577_INT1_ADCLOW_MASK, },
149 { .reg_offset = 0, .mask = MAX14577_INT1_ADCERR_MASK, },
150 { .reg_offset = 0, .mask = MAX77836_INT1_ADC1K_MASK, },
150 /* INT2 interrupts */
151 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
152 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
153 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
154 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
155 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
156 { .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, },
157 /* INT3 interrupts */

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151 /* INT2 interrupts */
152 { .reg_offset = 1, .mask = MAX14577_INT2_CHGTYP_MASK, },
153 { .reg_offset = 1, .mask = MAX14577_INT2_CHGDETRUN_MASK, },
154 { .reg_offset = 1, .mask = MAX14577_INT2_DCDTMR_MASK, },
155 { .reg_offset = 1, .mask = MAX14577_INT2_DBCHG_MASK, },
156 { .reg_offset = 1, .mask = MAX14577_INT2_VBVOLT_MASK, },
157 { .reg_offset = 1, .mask = MAX77836_INT2_VIDRM_MASK, },
158 /* INT3 interrupts */

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