da9063-irq.c (7494de0454af50215bc46c93c83b88a32ca39fab) da9063-irq.c (8b55734dc8bdc2327d78fcace3811e64a7c7cfec)
1/* da9063-irq.c: Interrupts support for Dialog DA9063
2 *
3 * Copyright 2012 Dialog Semiconductor Ltd.
4 * Copyright 2013 Philipp Zabel, Pengutronix
5 *
6 * Author: Michal Hajduk, Dialog Semiconductor
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 14 unchanged lines hidden (view full) ---

23
24#define DA9063_REG_EVENT_A_OFFSET 0
25#define DA9063_REG_EVENT_B_OFFSET 1
26#define DA9063_REG_EVENT_C_OFFSET 2
27#define DA9063_REG_EVENT_D_OFFSET 3
28
29static const struct regmap_irq da9063_irqs[] = {
30 /* DA9063 event A register */
1/* da9063-irq.c: Interrupts support for Dialog DA9063
2 *
3 * Copyright 2012 Dialog Semiconductor Ltd.
4 * Copyright 2013 Philipp Zabel, Pengutronix
5 *
6 * Author: Michal Hajduk, Dialog Semiconductor
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 14 unchanged lines hidden (view full) ---

23
24#define DA9063_REG_EVENT_A_OFFSET 0
25#define DA9063_REG_EVENT_B_OFFSET 1
26#define DA9063_REG_EVENT_C_OFFSET 2
27#define DA9063_REG_EVENT_D_OFFSET 3
28
29static const struct regmap_irq da9063_irqs[] = {
30 /* DA9063 event A register */
31 [DA9063_IRQ_ONKEY] = {
32 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
33 .mask = DA9063_M_ONKEY,
34 },
35 [DA9063_IRQ_ALARM] = {
36 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
37 .mask = DA9063_M_ALARM,
38 },
39 [DA9063_IRQ_TICK] = {
40 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
41 .mask = DA9063_M_TICK,
42 },
43 [DA9063_IRQ_ADC_RDY] = {
44 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
45 .mask = DA9063_M_ADC_RDY,
46 },
47 [DA9063_IRQ_SEQ_RDY] = {
48 .reg_offset = DA9063_REG_EVENT_A_OFFSET,
49 .mask = DA9063_M_SEQ_RDY,
50 },
31 REGMAP_IRQ_REG(DA9063_IRQ_ONKEY,
32 DA9063_REG_EVENT_A_OFFSET, DA9063_M_ONKEY),
33 REGMAP_IRQ_REG(DA9063_IRQ_ALARM,
34 DA9063_REG_EVENT_A_OFFSET, DA9063_M_ALARM),
35 REGMAP_IRQ_REG(DA9063_IRQ_TICK,
36 DA9063_REG_EVENT_A_OFFSET, DA9063_M_TICK),
37 REGMAP_IRQ_REG(DA9063_IRQ_ADC_RDY,
38 DA9063_REG_EVENT_A_OFFSET, DA9063_M_ADC_RDY),
39 REGMAP_IRQ_REG(DA9063_IRQ_SEQ_RDY,
40 DA9063_REG_EVENT_A_OFFSET, DA9063_M_SEQ_RDY),
51 /* DA9063 event B register */
41 /* DA9063 event B register */
52 [DA9063_IRQ_WAKE] = {
53 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
54 .mask = DA9063_M_WAKE,
55 },
56 [DA9063_IRQ_TEMP] = {
57 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
58 .mask = DA9063_M_TEMP,
59 },
60 [DA9063_IRQ_COMP_1V2] = {
61 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
62 .mask = DA9063_M_COMP_1V2,
63 },
64 [DA9063_IRQ_LDO_LIM] = {
65 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
66 .mask = DA9063_M_LDO_LIM,
67 },
68 [DA9063_IRQ_REG_UVOV] = {
69 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
70 .mask = DA9063_M_UVOV,
71 },
72 [DA9063_IRQ_DVC_RDY] = {
73 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
74 .mask = DA9063_M_DVC_RDY,
75 },
76 [DA9063_IRQ_VDD_MON] = {
77 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
78 .mask = DA9063_M_VDD_MON,
79 },
80 [DA9063_IRQ_WARN] = {
81 .reg_offset = DA9063_REG_EVENT_B_OFFSET,
82 .mask = DA9063_M_VDD_WARN,
83 },
42 REGMAP_IRQ_REG(DA9063_IRQ_WAKE,
43 DA9063_REG_EVENT_B_OFFSET, DA9063_M_WAKE),
44 REGMAP_IRQ_REG(DA9063_IRQ_TEMP,
45 DA9063_REG_EVENT_B_OFFSET, DA9063_M_TEMP),
46 REGMAP_IRQ_REG(DA9063_IRQ_COMP_1V2,
47 DA9063_REG_EVENT_B_OFFSET, DA9063_M_COMP_1V2),
48 REGMAP_IRQ_REG(DA9063_IRQ_LDO_LIM,
49 DA9063_REG_EVENT_B_OFFSET, DA9063_M_LDO_LIM),
50 REGMAP_IRQ_REG(DA9063_IRQ_REG_UVOV,
51 DA9063_REG_EVENT_B_OFFSET, DA9063_M_UVOV),
52 REGMAP_IRQ_REG(DA9063_IRQ_DVC_RDY,
53 DA9063_REG_EVENT_B_OFFSET, DA9063_M_DVC_RDY),
54 REGMAP_IRQ_REG(DA9063_IRQ_VDD_MON,
55 DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_MON),
56 REGMAP_IRQ_REG(DA9063_IRQ_WARN,
57 DA9063_REG_EVENT_B_OFFSET, DA9063_M_VDD_WARN),
84 /* DA9063 event C register */
58 /* DA9063 event C register */
85 [DA9063_IRQ_GPI0] = {
86 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
87 .mask = DA9063_M_GPI0,
88 },
89 [DA9063_IRQ_GPI1] = {
90 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
91 .mask = DA9063_M_GPI1,
92 },
93 [DA9063_IRQ_GPI2] = {
94 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
95 .mask = DA9063_M_GPI2,
96 },
97 [DA9063_IRQ_GPI3] = {
98 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
99 .mask = DA9063_M_GPI3,
100 },
101 [DA9063_IRQ_GPI4] = {
102 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
103 .mask = DA9063_M_GPI4,
104 },
105 [DA9063_IRQ_GPI5] = {
106 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
107 .mask = DA9063_M_GPI5,
108 },
109 [DA9063_IRQ_GPI6] = {
110 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
111 .mask = DA9063_M_GPI6,
112 },
113 [DA9063_IRQ_GPI7] = {
114 .reg_offset = DA9063_REG_EVENT_C_OFFSET,
115 .mask = DA9063_M_GPI7,
116 },
59 REGMAP_IRQ_REG(DA9063_IRQ_GPI0,
60 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI0),
61 REGMAP_IRQ_REG(DA9063_IRQ_GPI1,
62 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI1),
63 REGMAP_IRQ_REG(DA9063_IRQ_GPI2,
64 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI2),
65 REGMAP_IRQ_REG(DA9063_IRQ_GPI3,
66 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI3),
67 REGMAP_IRQ_REG(DA9063_IRQ_GPI4,
68 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI4),
69 REGMAP_IRQ_REG(DA9063_IRQ_GPI5,
70 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI5),
71 REGMAP_IRQ_REG(DA9063_IRQ_GPI6,
72 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI6),
73 REGMAP_IRQ_REG(DA9063_IRQ_GPI7,
74 DA9063_REG_EVENT_C_OFFSET, DA9063_M_GPI7),
117 /* DA9063 event D register */
75 /* DA9063 event D register */
118 [DA9063_IRQ_GPI8] = {
119 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
120 .mask = DA9063_M_GPI8,
121 },
122 [DA9063_IRQ_GPI9] = {
123 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
124 .mask = DA9063_M_GPI9,
125 },
126 [DA9063_IRQ_GPI10] = {
127 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
128 .mask = DA9063_M_GPI10,
129 },
130 [DA9063_IRQ_GPI11] = {
131 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
132 .mask = DA9063_M_GPI11,
133 },
134 [DA9063_IRQ_GPI12] = {
135 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
136 .mask = DA9063_M_GPI12,
137 },
138 [DA9063_IRQ_GPI13] = {
139 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
140 .mask = DA9063_M_GPI13,
141 },
142 [DA9063_IRQ_GPI14] = {
143 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
144 .mask = DA9063_M_GPI14,
145 },
146 [DA9063_IRQ_GPI15] = {
147 .reg_offset = DA9063_REG_EVENT_D_OFFSET,
148 .mask = DA9063_M_GPI15,
149 },
76 REGMAP_IRQ_REG(DA9063_IRQ_GPI8,
77 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI8),
78 REGMAP_IRQ_REG(DA9063_IRQ_GPI9,
79 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI9),
80 REGMAP_IRQ_REG(DA9063_IRQ_GPI10,
81 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI10),
82 REGMAP_IRQ_REG(DA9063_IRQ_GPI11,
83 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI11),
84 REGMAP_IRQ_REG(DA9063_IRQ_GPI12,
85 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI12),
86 REGMAP_IRQ_REG(DA9063_IRQ_GPI13,
87 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI13),
88 REGMAP_IRQ_REG(DA9063_IRQ_GPI14,
89 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI14),
90 REGMAP_IRQ_REG(DA9063_IRQ_GPI15,
91 DA9063_REG_EVENT_D_OFFSET, DA9063_M_GPI15),
150};
151
152static const struct regmap_irq_chip da9063_irq_chip = {
153 .name = "da9063-irq",
154 .irqs = da9063_irqs,
155 .num_irqs = DA9063_NUM_IRQ,
92};
93
94static const struct regmap_irq_chip da9063_irq_chip = {
95 .name = "da9063-irq",
96 .irqs = da9063_irqs,
97 .num_irqs = DA9063_NUM_IRQ,
156
157 .num_regs = 4,
158 .status_base = DA9063_REG_EVENT_A,
159 .mask_base = DA9063_REG_IRQ_MASK_A,
160 .ack_base = DA9063_REG_EVENT_A,
161 .init_ack_masked = true,
162};
163
164int da9063_irq_init(struct da9063 *da9063)

--- 21 unchanged lines hidden --- 		98 .num_regs = 4,
99 .status_base = DA9063_REG_EVENT_A,
100 .mask_base = DA9063_REG_IRQ_MASK_A,
101 .ack_base = DA9063_REG_EVENT_A,
102 .init_ack_masked = true,
103};
104
105int da9063_irq_init(struct da9063 *da9063)

--- 21 unchanged lines hidden ---