tegra186.c (7191b623a238f8859f70defc227b85fa9bce18d4) tegra186.c (8fd9f632ba93c0291a73be25ddd3f22631cd1052)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/module.h>
8#include <linux/mod_devicetable.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11
12#include <soc/tegra/mc.h>
13
14#if defined(CONFIG_ARCH_TEGRA_186_SOC)
15#include <dt-bindings/memory/tegra186-mc.h>
16#endif
17
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/io.h>
7#include <linux/module.h>
8#include <linux/mod_devicetable.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11
12#include <soc/tegra/mc.h>
13
14#if defined(CONFIG_ARCH_TEGRA_186_SOC)
15#include <dt-bindings/memory/tegra186-mc.h>
16#endif
17
18#if defined(CONFIG_ARCH_TEGRA_194_SOC)
19#include <dt-bindings/memory/tegra194-mc.h>
20#endif
21
22static void tegra186_mc_program_sid(struct tegra_mc *mc)
23{
24 unsigned int i;
25
26 for (i = 0; i < mc->soc->num_clients; i++) {
27 const struct tegra_mc_client *client = &mc->soc->clients[i];
28 u32 override, security;
29

--- 35 unchanged lines hidden (view full) ---

65
66static int tegra186_mc_resume(struct tegra_mc *mc)
67{
68 tegra186_mc_program_sid(mc);
69
70 return 0;
71}
72
18static void tegra186_mc_program_sid(struct tegra_mc *mc)
19{
20 unsigned int i;
21
22 for (i = 0; i < mc->soc->num_clients; i++) {
23 const struct tegra_mc_client *client = &mc->soc->clients[i];
24 u32 override, security;
25

--- 35 unchanged lines hidden (view full) ---

61
62static int tegra186_mc_resume(struct tegra_mc *mc)
63{
64 tegra186_mc_program_sid(mc);
65
66 return 0;
67}
68
73static const struct tegra_mc_ops tegra186_mc_ops = {
69const struct tegra_mc_ops tegra186_mc_ops = {
74 .probe = tegra186_mc_probe,
75 .remove = tegra186_mc_remove,
76 .resume = tegra186_mc_resume,
77};
78
79#if defined(CONFIG_ARCH_TEGRA_186_SOC)
80static const struct tegra_mc_client tegra186_mc_clients[] = {
81 {

--- 721 unchanged lines hidden (view full) ---

803
804const struct tegra_mc_soc tegra186_mc_soc = {
805 .num_clients = ARRAY_SIZE(tegra186_mc_clients),
806 .clients = tegra186_mc_clients,
807 .num_address_bits = 40,
808 .ops = &tegra186_mc_ops,
809};
810#endif
70 .probe = tegra186_mc_probe,
71 .remove = tegra186_mc_remove,
72 .resume = tegra186_mc_resume,
73};
74
75#if defined(CONFIG_ARCH_TEGRA_186_SOC)
76static const struct tegra_mc_client tegra186_mc_clients[] = {
77 {

--- 721 unchanged lines hidden (view full) ---

799
800const struct tegra_mc_soc tegra186_mc_soc = {
801 .num_clients = ARRAY_SIZE(tegra186_mc_clients),
802 .clients = tegra186_mc_clients,
803 .num_address_bits = 40,
804 .ops = &tegra186_mc_ops,
805};
806#endif
811
812#if defined(CONFIG_ARCH_TEGRA_194_SOC)
813static const struct tegra_mc_client tegra194_mc_clients[] = {
814 {
815 .id = TEGRA194_MEMORY_CLIENT_PTCR,
816 .name = "ptcr",
817 .sid = TEGRA194_SID_PASSTHROUGH,
818 .regs = {
819 .sid = {
820 .override = 0x000,
821 .security = 0x004,
822 },
823 },
824 }, {
825 .id = TEGRA194_MEMORY_CLIENT_MIU7R,
826 .name = "miu7r",
827 .sid = TEGRA194_SID_MIU,
828 .regs = {
829 .sid = {
830 .override = 0x008,
831 .security = 0x00c,
832 },
833 },
834 }, {
835 .id = TEGRA194_MEMORY_CLIENT_MIU7W,
836 .name = "miu7w",
837 .sid = TEGRA194_SID_MIU,
838 .regs = {
839 .sid = {
840 .override = 0x010,
841 .security = 0x014,
842 },
843 },
844 }, {
845 .id = TEGRA194_MEMORY_CLIENT_HDAR,
846 .name = "hdar",
847 .sid = TEGRA194_SID_HDA,
848 .regs = {
849 .sid = {
850 .override = 0x0a8,
851 .security = 0x0ac,
852 },
853 },
854 }, {
855 .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
856 .name = "host1xdmar",
857 .sid = TEGRA194_SID_HOST1X,
858 .regs = {
859 .sid = {
860 .override = 0x0b0,
861 .security = 0x0b4,
862 },
863 },
864 }, {
865 .id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
866 .name = "nvencsrd",
867 .sid = TEGRA194_SID_NVENC,
868 .regs = {
869 .sid = {
870 .override = 0x0e0,
871 .security = 0x0e4,
872 },
873 },
874 }, {
875 .id = TEGRA194_MEMORY_CLIENT_SATAR,
876 .name = "satar",
877 .sid = TEGRA194_SID_SATA,
878 .regs = {
879 .sid = {
880 .override = 0x0f8,
881 .security = 0x0fc,
882 },
883 },
884 }, {
885 .id = TEGRA194_MEMORY_CLIENT_MPCORER,
886 .name = "mpcorer",
887 .sid = TEGRA194_SID_PASSTHROUGH,
888 .regs = {
889 .sid = {
890 .override = 0x138,
891 .security = 0x13c,
892 },
893 },
894 }, {
895 .id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
896 .name = "nvencswr",
897 .sid = TEGRA194_SID_NVENC,
898 .regs = {
899 .sid = {
900 .override = 0x158,
901 .security = 0x15c,
902 },
903 },
904 }, {
905 .id = TEGRA194_MEMORY_CLIENT_HDAW,
906 .name = "hdaw",
907 .sid = TEGRA194_SID_HDA,
908 .regs = {
909 .sid = {
910 .override = 0x1a8,
911 .security = 0x1ac,
912 },
913 },
914 }, {
915 .id = TEGRA194_MEMORY_CLIENT_MPCOREW,
916 .name = "mpcorew",
917 .sid = TEGRA194_SID_PASSTHROUGH,
918 .regs = {
919 .sid = {
920 .override = 0x1c8,
921 .security = 0x1cc,
922 },
923 },
924 }, {
925 .id = TEGRA194_MEMORY_CLIENT_SATAW,
926 .name = "sataw",
927 .sid = TEGRA194_SID_SATA,
928 .regs = {
929 .sid = {
930 .override = 0x1e8,
931 .security = 0x1ec,
932 },
933 },
934 }, {
935 .id = TEGRA194_MEMORY_CLIENT_ISPRA,
936 .name = "ispra",
937 .sid = TEGRA194_SID_ISP,
938 .regs = {
939 .sid = {
940 .override = 0x220,
941 .security = 0x224,
942 },
943 },
944 }, {
945 .id = TEGRA194_MEMORY_CLIENT_ISPFALR,
946 .name = "ispfalr",
947 .sid = TEGRA194_SID_ISP_FALCON,
948 .regs = {
949 .sid = {
950 .override = 0x228,
951 .security = 0x22c,
952 },
953 },
954 }, {
955 .id = TEGRA194_MEMORY_CLIENT_ISPWA,
956 .name = "ispwa",
957 .sid = TEGRA194_SID_ISP,
958 .regs = {
959 .sid = {
960 .override = 0x230,
961 .security = 0x234,
962 },
963 },
964 }, {
965 .id = TEGRA194_MEMORY_CLIENT_ISPWB,
966 .name = "ispwb",
967 .sid = TEGRA194_SID_ISP,
968 .regs = {
969 .sid = {
970 .override = 0x238,
971 .security = 0x23c,
972 },
973 },
974 }, {
975 .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR,
976 .name = "xusb_hostr",
977 .sid = TEGRA194_SID_XUSB_HOST,
978 .regs = {
979 .sid = {
980 .override = 0x250,
981 .security = 0x254,
982 },
983 },
984 }, {
985 .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW,
986 .name = "xusb_hostw",
987 .sid = TEGRA194_SID_XUSB_HOST,
988 .regs = {
989 .sid = {
990 .override = 0x258,
991 .security = 0x25c,
992 },
993 },
994 }, {
995 .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR,
996 .name = "xusb_devr",
997 .sid = TEGRA194_SID_XUSB_DEV,
998 .regs = {
999 .sid = {
1000 .override = 0x260,
1001 .security = 0x264,
1002 },
1003 },
1004 }, {
1005 .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW,
1006 .name = "xusb_devw",
1007 .sid = TEGRA194_SID_XUSB_DEV,
1008 .regs = {
1009 .sid = {
1010 .override = 0x268,
1011 .security = 0x26c,
1012 },
1013 },
1014 }, {
1015 .id = TEGRA194_MEMORY_CLIENT_SDMMCRA,
1016 .name = "sdmmcra",
1017 .sid = TEGRA194_SID_SDMMC1,
1018 .regs = {
1019 .sid = {
1020 .override = 0x300,
1021 .security = 0x304,
1022 },
1023 },
1024 }, {
1025 .id = TEGRA194_MEMORY_CLIENT_SDMMCR,
1026 .name = "sdmmcr",
1027 .sid = TEGRA194_SID_SDMMC3,
1028 .regs = {
1029 .sid = {
1030 .override = 0x310,
1031 .security = 0x314,
1032 },
1033 },
1034 }, {
1035 .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB,
1036 .name = "sdmmcrab",
1037 .sid = TEGRA194_SID_SDMMC4,
1038 .regs = {
1039 .sid = {
1040 .override = 0x318,
1041 .security = 0x31c,
1042 },
1043 },
1044 }, {
1045 .id = TEGRA194_MEMORY_CLIENT_SDMMCWA,
1046 .name = "sdmmcwa",
1047 .sid = TEGRA194_SID_SDMMC1,
1048 .regs = {
1049 .sid = {
1050 .override = 0x320,
1051 .security = 0x324,
1052 },
1053 },
1054 }, {
1055 .id = TEGRA194_MEMORY_CLIENT_SDMMCW,
1056 .name = "sdmmcw",
1057 .sid = TEGRA194_SID_SDMMC3,
1058 .regs = {
1059 .sid = {
1060 .override = 0x330,
1061 .security = 0x334,
1062 },
1063 },
1064 }, {
1065 .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB,
1066 .name = "sdmmcwab",
1067 .sid = TEGRA194_SID_SDMMC4,
1068 .regs = {
1069 .sid = {
1070 .override = 0x338,
1071 .security = 0x33c,
1072 },
1073 },
1074 }, {
1075 .id = TEGRA194_MEMORY_CLIENT_VICSRD,
1076 .name = "vicsrd",
1077 .sid = TEGRA194_SID_VIC,
1078 .regs = {
1079 .sid = {
1080 .override = 0x360,
1081 .security = 0x364,
1082 },
1083 },
1084 }, {
1085 .id = TEGRA194_MEMORY_CLIENT_VICSWR,
1086 .name = "vicswr",
1087 .sid = TEGRA194_SID_VIC,
1088 .regs = {
1089 .sid = {
1090 .override = 0x368,
1091 .security = 0x36c,
1092 },
1093 },
1094 }, {
1095 .id = TEGRA194_MEMORY_CLIENT_VIW,
1096 .name = "viw",
1097 .sid = TEGRA194_SID_VI,
1098 .regs = {
1099 .sid = {
1100 .override = 0x390,
1101 .security = 0x394,
1102 },
1103 },
1104 }, {
1105 .id = TEGRA194_MEMORY_CLIENT_NVDECSRD,
1106 .name = "nvdecsrd",
1107 .sid = TEGRA194_SID_NVDEC,
1108 .regs = {
1109 .sid = {
1110 .override = 0x3c0,
1111 .security = 0x3c4,
1112 },
1113 },
1114 }, {
1115 .id = TEGRA194_MEMORY_CLIENT_NVDECSWR,
1116 .name = "nvdecswr",
1117 .sid = TEGRA194_SID_NVDEC,
1118 .regs = {
1119 .sid = {
1120 .override = 0x3c8,
1121 .security = 0x3cc,
1122 },
1123 },
1124 }, {
1125 .id = TEGRA194_MEMORY_CLIENT_APER,
1126 .name = "aper",
1127 .sid = TEGRA194_SID_APE,
1128 .regs = {
1129 .sid = {
1130 .override = 0x3c0,
1131 .security = 0x3c4,
1132 },
1133 },
1134 }, {
1135 .id = TEGRA194_MEMORY_CLIENT_APEW,
1136 .name = "apew",
1137 .sid = TEGRA194_SID_APE,
1138 .regs = {
1139 .sid = {
1140 .override = 0x3d0,
1141 .security = 0x3d4,
1142 },
1143 },
1144 }, {
1145 .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD,
1146 .name = "nvjpgsrd",
1147 .sid = TEGRA194_SID_NVJPG,
1148 .regs = {
1149 .sid = {
1150 .override = 0x3f0,
1151 .security = 0x3f4,
1152 },
1153 },
1154 }, {
1155 .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR,
1156 .name = "nvjpgswr",
1157 .sid = TEGRA194_SID_NVJPG,
1158 .regs = {
1159 .sid = {
1160 .override = 0x3f0,
1161 .security = 0x3f4,
1162 },
1163 },
1164 }, {
1165 .name = "axiapr",
1166 .id = TEGRA194_MEMORY_CLIENT_AXIAPR,
1167 .sid = TEGRA194_SID_PASSTHROUGH,
1168 .regs = {
1169 .sid = {
1170 .override = 0x410,
1171 .security = 0x414,
1172 },
1173 },
1174 }, {
1175 .id = TEGRA194_MEMORY_CLIENT_AXIAPW,
1176 .name = "axiapw",
1177 .sid = TEGRA194_SID_PASSTHROUGH,
1178 .regs = {
1179 .sid = {
1180 .override = 0x418,
1181 .security = 0x41c,
1182 },
1183 },
1184 }, {
1185 .id = TEGRA194_MEMORY_CLIENT_ETRR,
1186 .name = "etrr",
1187 .sid = TEGRA194_SID_ETR,
1188 .regs = {
1189 .sid = {
1190 .override = 0x420,
1191 .security = 0x424,
1192 },
1193 },
1194 }, {
1195 .id = TEGRA194_MEMORY_CLIENT_ETRW,
1196 .name = "etrw",
1197 .sid = TEGRA194_SID_ETR,
1198 .regs = {
1199 .sid = {
1200 .override = 0x428,
1201 .security = 0x42c,
1202 },
1203 },
1204 }, {
1205 .id = TEGRA194_MEMORY_CLIENT_AXISR,
1206 .name = "axisr",
1207 .sid = TEGRA194_SID_PASSTHROUGH,
1208 .regs = {
1209 .sid = {
1210 .override = 0x460,
1211 .security = 0x464,
1212 },
1213 },
1214 }, {
1215 .id = TEGRA194_MEMORY_CLIENT_AXISW,
1216 .name = "axisw",
1217 .sid = TEGRA194_SID_PASSTHROUGH,
1218 .regs = {
1219 .sid = {
1220 .override = 0x468,
1221 .security = 0x46c,
1222 },
1223 },
1224 }, {
1225 .id = TEGRA194_MEMORY_CLIENT_EQOSR,
1226 .name = "eqosr",
1227 .sid = TEGRA194_SID_EQOS,
1228 .regs = {
1229 .sid = {
1230 .override = 0x470,
1231 .security = 0x474,
1232 },
1233 },
1234 }, {
1235 .name = "eqosw",
1236 .id = TEGRA194_MEMORY_CLIENT_EQOSW,
1237 .sid = TEGRA194_SID_EQOS,
1238 .regs = {
1239 .sid = {
1240 .override = 0x478,
1241 .security = 0x47c,
1242 },
1243 },
1244 }, {
1245 .id = TEGRA194_MEMORY_CLIENT_UFSHCR,
1246 .name = "ufshcr",
1247 .sid = TEGRA194_SID_UFSHC,
1248 .regs = {
1249 .sid = {
1250 .override = 0x480,
1251 .security = 0x484,
1252 },
1253 },
1254 }, {
1255 .id = TEGRA194_MEMORY_CLIENT_UFSHCW,
1256 .name = "ufshcw",
1257 .sid = TEGRA194_SID_UFSHC,
1258 .regs = {
1259 .sid = {
1260 .override = 0x488,
1261 .security = 0x48c,
1262 },
1263 },
1264 }, {
1265 .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR,
1266 .name = "nvdisplayr",
1267 .sid = TEGRA194_SID_NVDISPLAY,
1268 .regs = {
1269 .sid = {
1270 .override = 0x490,
1271 .security = 0x494,
1272 },
1273 },
1274 }, {
1275 .id = TEGRA194_MEMORY_CLIENT_BPMPR,
1276 .name = "bpmpr",
1277 .sid = TEGRA194_SID_BPMP,
1278 .regs = {
1279 .sid = {
1280 .override = 0x498,
1281 .security = 0x49c,
1282 },
1283 },
1284 }, {
1285 .id = TEGRA194_MEMORY_CLIENT_BPMPW,
1286 .name = "bpmpw",
1287 .sid = TEGRA194_SID_BPMP,
1288 .regs = {
1289 .sid = {
1290 .override = 0x4a0,
1291 .security = 0x4a4,
1292 },
1293 },
1294 }, {
1295 .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR,
1296 .name = "bpmpdmar",
1297 .sid = TEGRA194_SID_BPMP,
1298 .regs = {
1299 .sid = {
1300 .override = 0x4a8,
1301 .security = 0x4ac,
1302 },
1303 },
1304 }, {
1305 .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW,
1306 .name = "bpmpdmaw",
1307 .sid = TEGRA194_SID_BPMP,
1308 .regs = {
1309 .sid = {
1310 .override = 0x4b0,
1311 .security = 0x4b4,
1312 },
1313 },
1314 }, {
1315 .id = TEGRA194_MEMORY_CLIENT_AONR,
1316 .name = "aonr",
1317 .sid = TEGRA194_SID_AON,
1318 .regs = {
1319 .sid = {
1320 .override = 0x4b8,
1321 .security = 0x4bc,
1322 },
1323 },
1324 }, {
1325 .id = TEGRA194_MEMORY_CLIENT_AONW,
1326 .name = "aonw",
1327 .sid = TEGRA194_SID_AON,
1328 .regs = {
1329 .sid = {
1330 .override = 0x4c0,
1331 .security = 0x4c4,
1332 },
1333 },
1334 }, {
1335 .id = TEGRA194_MEMORY_CLIENT_AONDMAR,
1336 .name = "aondmar",
1337 .sid = TEGRA194_SID_AON,
1338 .regs = {
1339 .sid = {
1340 .override = 0x4c8,
1341 .security = 0x4cc,
1342 },
1343 },
1344 }, {
1345 .id = TEGRA194_MEMORY_CLIENT_AONDMAW,
1346 .name = "aondmaw",
1347 .sid = TEGRA194_SID_AON,
1348 .regs = {
1349 .sid = {
1350 .override = 0x4d0,
1351 .security = 0x4d4,
1352 },
1353 },
1354 }, {
1355 .id = TEGRA194_MEMORY_CLIENT_SCER,
1356 .name = "scer",
1357 .sid = TEGRA194_SID_SCE,
1358 .regs = {
1359 .sid = {
1360 .override = 0x4d8,
1361 .security = 0x4dc,
1362 },
1363 },
1364 }, {
1365 .id = TEGRA194_MEMORY_CLIENT_SCEW,
1366 .name = "scew",
1367 .sid = TEGRA194_SID_SCE,
1368 .regs = {
1369 .sid = {
1370 .override = 0x4e0,
1371 .security = 0x4e4,
1372 },
1373 },
1374 }, {
1375 .id = TEGRA194_MEMORY_CLIENT_SCEDMAR,
1376 .name = "scedmar",
1377 .sid = TEGRA194_SID_SCE,
1378 .regs = {
1379 .sid = {
1380 .override = 0x4e8,
1381 .security = 0x4ec,
1382 },
1383 },
1384 }, {
1385 .id = TEGRA194_MEMORY_CLIENT_SCEDMAW,
1386 .name = "scedmaw",
1387 .sid = TEGRA194_SID_SCE,
1388 .regs = {
1389 .sid = {
1390 .override = 0x4f0,
1391 .security = 0x4f4,
1392 },
1393 },
1394 }, {
1395 .id = TEGRA194_MEMORY_CLIENT_APEDMAR,
1396 .name = "apedmar",
1397 .sid = TEGRA194_SID_APE,
1398 .regs = {
1399 .sid = {
1400 .override = 0x4f8,
1401 .security = 0x4fc,
1402 },
1403 },
1404 }, {
1405 .id = TEGRA194_MEMORY_CLIENT_APEDMAW,
1406 .name = "apedmaw",
1407 .sid = TEGRA194_SID_APE,
1408 .regs = {
1409 .sid = {
1410 .override = 0x500,
1411 .security = 0x504,
1412 },
1413 },
1414 }, {
1415 .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1,
1416 .name = "nvdisplayr1",
1417 .sid = TEGRA194_SID_NVDISPLAY,
1418 .regs = {
1419 .sid = {
1420 .override = 0x508,
1421 .security = 0x50c,
1422 },
1423 },
1424 }, {
1425 .id = TEGRA194_MEMORY_CLIENT_VICSRD1,
1426 .name = "vicsrd1",
1427 .sid = TEGRA194_SID_VIC,
1428 .regs = {
1429 .sid = {
1430 .override = 0x510,
1431 .security = 0x514,
1432 },
1433 },
1434 }, {
1435 .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1,
1436 .name = "nvdecsrd1",
1437 .sid = TEGRA194_SID_NVDEC,
1438 .regs = {
1439 .sid = {
1440 .override = 0x518,
1441 .security = 0x51c,
1442 },
1443 },
1444 }, {
1445 .id = TEGRA194_MEMORY_CLIENT_MIU0R,
1446 .name = "miu0r",
1447 .sid = TEGRA194_SID_MIU,
1448 .regs = {
1449 .sid = {
1450 .override = 0x530,
1451 .security = 0x534,
1452 },
1453 },
1454 }, {
1455 .name = "miu0w",
1456 .id = TEGRA194_MEMORY_CLIENT_MIU0W,
1457 .sid = TEGRA194_SID_MIU,
1458 .regs = {
1459 .sid = {
1460 .override = 0x538,
1461 .security = 0x53c,
1462 },
1463 },
1464 }, {
1465 .id = TEGRA194_MEMORY_CLIENT_MIU1R,
1466 .name = "miu1r",
1467 .sid = TEGRA194_SID_MIU,
1468 .regs = {
1469 .sid = {
1470 .override = 0x540,
1471 .security = 0x544,
1472 },
1473 },
1474 }, {
1475 .id = TEGRA194_MEMORY_CLIENT_MIU1W,
1476 .name = "miu1w",
1477 .sid = TEGRA194_SID_MIU,
1478 .regs = {
1479 .sid = {
1480 .override = 0x548,
1481 .security = 0x54c,
1482 },
1483 },
1484 }, {
1485 .id = TEGRA194_MEMORY_CLIENT_MIU2R,
1486 .name = "miu2r",
1487 .sid = TEGRA194_SID_MIU,
1488 .regs = {
1489 .sid = {
1490 .override = 0x570,
1491 .security = 0x574,
1492 },
1493 },
1494 }, {
1495 .id = TEGRA194_MEMORY_CLIENT_MIU2W,
1496 .name = "miu2w",
1497 .sid = TEGRA194_SID_MIU,
1498 .regs = {
1499 .sid = {
1500 .override = 0x578,
1501 .security = 0x57c,
1502 },
1503 },
1504 }, {
1505 .id = TEGRA194_MEMORY_CLIENT_MIU3R,
1506 .name = "miu3r",
1507 .sid = TEGRA194_SID_MIU,
1508 .regs = {
1509 .sid = {
1510 .override = 0x580,
1511 .security = 0x584,
1512 },
1513 },
1514 }, {
1515 .id = TEGRA194_MEMORY_CLIENT_MIU3W,
1516 .name = "miu3w",
1517 .sid = TEGRA194_SID_MIU,
1518 .regs = {
1519 .sid = {
1520 .override = 0x588,
1521 .security = 0x58c,
1522 },
1523 },
1524 }, {
1525 .id = TEGRA194_MEMORY_CLIENT_MIU4R,
1526 .name = "miu4r",
1527 .sid = TEGRA194_SID_MIU,
1528 .regs = {
1529 .sid = {
1530 .override = 0x590,
1531 .security = 0x594,
1532 },
1533 },
1534 }, {
1535 .id = TEGRA194_MEMORY_CLIENT_MIU4W,
1536 .name = "miu4w",
1537 .sid = TEGRA194_SID_MIU,
1538 .regs = {
1539 .sid = {
1540 .override = 0x598,
1541 .security = 0x59c,
1542 },
1543 },
1544 }, {
1545 .id = TEGRA194_MEMORY_CLIENT_DPMUR,
1546 .name = "dpmur",
1547 .sid = TEGRA194_SID_PASSTHROUGH,
1548 .regs = {
1549 .sid = {
1550 .override = 0x598,
1551 .security = 0x59c,
1552 },
1553 },
1554 }, {
1555 .id = TEGRA194_MEMORY_CLIENT_VIFALR,
1556 .name = "vifalr",
1557 .sid = TEGRA194_SID_VI_FALCON,
1558 .regs = {
1559 .sid = {
1560 .override = 0x5e0,
1561 .security = 0x5e4,
1562 },
1563 },
1564 }, {
1565 .id = TEGRA194_MEMORY_CLIENT_VIFALW,
1566 .name = "vifalw",
1567 .sid = TEGRA194_SID_VI_FALCON,
1568 .regs = {
1569 .sid = {
1570 .override = 0x5e8,
1571 .security = 0x5ec,
1572 },
1573 },
1574 }, {
1575 .id = TEGRA194_MEMORY_CLIENT_DLA0RDA,
1576 .name = "dla0rda",
1577 .sid = TEGRA194_SID_NVDLA0,
1578 .regs = {
1579 .sid = {
1580 .override = 0x5f0,
1581 .security = 0x5f4,
1582 },
1583 },
1584 }, {
1585 .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB,
1586 .name = "dla0falrdb",
1587 .sid = TEGRA194_SID_NVDLA0,
1588 .regs = {
1589 .sid = {
1590 .override = 0x5f8,
1591 .security = 0x5fc,
1592 },
1593 },
1594 }, {
1595 .id = TEGRA194_MEMORY_CLIENT_DLA0WRA,
1596 .name = "dla0wra",
1597 .sid = TEGRA194_SID_NVDLA0,
1598 .regs = {
1599 .sid = {
1600 .override = 0x600,
1601 .security = 0x604,
1602 },
1603 },
1604 }, {
1605 .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB,
1606 .name = "dla0falwrb",
1607 .sid = TEGRA194_SID_NVDLA0,
1608 .regs = {
1609 .sid = {
1610 .override = 0x608,
1611 .security = 0x60c,
1612 },
1613 },
1614 }, {
1615 .id = TEGRA194_MEMORY_CLIENT_DLA1RDA,
1616 .name = "dla1rda",
1617 .sid = TEGRA194_SID_NVDLA1,
1618 .regs = {
1619 .sid = {
1620 .override = 0x610,
1621 .security = 0x614,
1622 },
1623 },
1624 }, {
1625 .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB,
1626 .name = "dla1falrdb",
1627 .sid = TEGRA194_SID_NVDLA1,
1628 .regs = {
1629 .sid = {
1630 .override = 0x618,
1631 .security = 0x61c,
1632 },
1633 },
1634 }, {
1635 .id = TEGRA194_MEMORY_CLIENT_DLA1WRA,
1636 .name = "dla1wra",
1637 .sid = TEGRA194_SID_NVDLA1,
1638 .regs = {
1639 .sid = {
1640 .override = 0x620,
1641 .security = 0x624,
1642 },
1643 },
1644 }, {
1645 .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB,
1646 .name = "dla1falwrb",
1647 .sid = TEGRA194_SID_NVDLA1,
1648 .regs = {
1649 .sid = {
1650 .override = 0x628,
1651 .security = 0x62c,
1652 },
1653 },
1654 }, {
1655 .id = TEGRA194_MEMORY_CLIENT_PVA0RDA,
1656 .name = "pva0rda",
1657 .sid = TEGRA194_SID_PVA0,
1658 .regs = {
1659 .sid = {
1660 .override = 0x630,
1661 .security = 0x634,
1662 },
1663 },
1664 }, {
1665 .id = TEGRA194_MEMORY_CLIENT_PVA0RDB,
1666 .name = "pva0rdb",
1667 .sid = TEGRA194_SID_PVA0,
1668 .regs = {
1669 .sid = {
1670 .override = 0x638,
1671 .security = 0x63c,
1672 },
1673 },
1674 }, {
1675 .id = TEGRA194_MEMORY_CLIENT_PVA0RDC,
1676 .name = "pva0rdc",
1677 .sid = TEGRA194_SID_PVA0,
1678 .regs = {
1679 .sid = {
1680 .override = 0x640,
1681 .security = 0x644,
1682 },
1683 },
1684 }, {
1685 .id = TEGRA194_MEMORY_CLIENT_PVA0WRA,
1686 .name = "pva0wra",
1687 .sid = TEGRA194_SID_PVA0,
1688 .regs = {
1689 .sid = {
1690 .override = 0x648,
1691 .security = 0x64c,
1692 },
1693 },
1694 }, {
1695 .id = TEGRA194_MEMORY_CLIENT_PVA0WRB,
1696 .name = "pva0wrb",
1697 .sid = TEGRA194_SID_PVA0,
1698 .regs = {
1699 .sid = {
1700 .override = 0x650,
1701 .security = 0x654,
1702 },
1703 },
1704 }, {
1705 .id = TEGRA194_MEMORY_CLIENT_PVA0WRC,
1706 .name = "pva0wrc",
1707 .sid = TEGRA194_SID_PVA0,
1708 .regs = {
1709 .sid = {
1710 .override = 0x658,
1711 .security = 0x65c,
1712 },
1713 },
1714 }, {
1715 .id = TEGRA194_MEMORY_CLIENT_PVA1RDA,
1716 .name = "pva1rda",
1717 .sid = TEGRA194_SID_PVA1,
1718 .regs = {
1719 .sid = {
1720 .override = 0x660,
1721 .security = 0x664,
1722 },
1723 },
1724 }, {
1725 .id = TEGRA194_MEMORY_CLIENT_PVA1RDB,
1726 .name = "pva1rdb",
1727 .sid = TEGRA194_SID_PVA1,
1728 .regs = {
1729 .sid = {
1730 .override = 0x668,
1731 .security = 0x66c,
1732 },
1733 },
1734 }, {
1735 .id = TEGRA194_MEMORY_CLIENT_PVA1RDC,
1736 .name = "pva1rdc",
1737 .sid = TEGRA194_SID_PVA1,
1738 .regs = {
1739 .sid = {
1740 .override = 0x670,
1741 .security = 0x674,
1742 },
1743 },
1744 }, {
1745 .id = TEGRA194_MEMORY_CLIENT_PVA1WRA,
1746 .name = "pva1wra",
1747 .sid = TEGRA194_SID_PVA1,
1748 .regs = {
1749 .sid = {
1750 .override = 0x678,
1751 .security = 0x67c,
1752 },
1753 },
1754 }, {
1755 .id = TEGRA194_MEMORY_CLIENT_PVA1WRB,
1756 .name = "pva1wrb",
1757 .sid = TEGRA194_SID_PVA1,
1758 .regs = {
1759 .sid = {
1760 .override = 0x680,
1761 .security = 0x684,
1762 },
1763 },
1764 }, {
1765 .id = TEGRA194_MEMORY_CLIENT_PVA1WRC,
1766 .name = "pva1wrc",
1767 .sid = TEGRA194_SID_PVA1,
1768 .regs = {
1769 .sid = {
1770 .override = 0x688,
1771 .security = 0x68c,
1772 },
1773 },
1774 }, {
1775 .id = TEGRA194_MEMORY_CLIENT_RCER,
1776 .name = "rcer",
1777 .sid = TEGRA194_SID_RCE,
1778 .regs = {
1779 .sid = {
1780 .override = 0x690,
1781 .security = 0x694,
1782 },
1783 },
1784 }, {
1785 .id = TEGRA194_MEMORY_CLIENT_RCEW,
1786 .name = "rcew",
1787 .sid = TEGRA194_SID_RCE,
1788 .regs = {
1789 .sid = {
1790 .override = 0x698,
1791 .security = 0x69c,
1792 },
1793 },
1794 }, {
1795 .id = TEGRA194_MEMORY_CLIENT_RCEDMAR,
1796 .name = "rcedmar",
1797 .sid = TEGRA194_SID_RCE,
1798 .regs = {
1799 .sid = {
1800 .override = 0x6a0,
1801 .security = 0x6a4,
1802 },
1803 },
1804 }, {
1805 .id = TEGRA194_MEMORY_CLIENT_RCEDMAW,
1806 .name = "rcedmaw",
1807 .sid = TEGRA194_SID_RCE,
1808 .regs = {
1809 .sid = {
1810 .override = 0x6a8,
1811 .security = 0x6ac,
1812 },
1813 },
1814 }, {
1815 .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD,
1816 .name = "nvenc1srd",
1817 .sid = TEGRA194_SID_NVENC1,
1818 .regs = {
1819 .sid = {
1820 .override = 0x6b0,
1821 .security = 0x6b4,
1822 },
1823 },
1824 }, {
1825 .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR,
1826 .name = "nvenc1swr",
1827 .sid = TEGRA194_SID_NVENC1,
1828 .regs = {
1829 .sid = {
1830 .override = 0x6b8,
1831 .security = 0x6bc,
1832 },
1833 },
1834 }, {
1835 .id = TEGRA194_MEMORY_CLIENT_PCIE0R,
1836 .name = "pcie0r",
1837 .sid = TEGRA194_SID_PCIE0,
1838 .regs = {
1839 .sid = {
1840 .override = 0x6c0,
1841 .security = 0x6c4,
1842 },
1843 },
1844 }, {
1845 .id = TEGRA194_MEMORY_CLIENT_PCIE0W,
1846 .name = "pcie0w",
1847 .sid = TEGRA194_SID_PCIE0,
1848 .regs = {
1849 .sid = {
1850 .override = 0x6c8,
1851 .security = 0x6cc,
1852 },
1853 },
1854 }, {
1855 .id = TEGRA194_MEMORY_CLIENT_PCIE1R,
1856 .name = "pcie1r",
1857 .sid = TEGRA194_SID_PCIE1,
1858 .regs = {
1859 .sid = {
1860 .override = 0x6d0,
1861 .security = 0x6d4,
1862 },
1863 },
1864 }, {
1865 .id = TEGRA194_MEMORY_CLIENT_PCIE1W,
1866 .name = "pcie1w",
1867 .sid = TEGRA194_SID_PCIE1,
1868 .regs = {
1869 .sid = {
1870 .override = 0x6d8,
1871 .security = 0x6dc,
1872 },
1873 },
1874 }, {
1875 .id = TEGRA194_MEMORY_CLIENT_PCIE2AR,
1876 .name = "pcie2ar",
1877 .sid = TEGRA194_SID_PCIE2,
1878 .regs = {
1879 .sid = {
1880 .override = 0x6e0,
1881 .security = 0x6e4,
1882 },
1883 },
1884 }, {
1885 .id = TEGRA194_MEMORY_CLIENT_PCIE2AW,
1886 .name = "pcie2aw",
1887 .sid = TEGRA194_SID_PCIE2,
1888 .regs = {
1889 .sid = {
1890 .override = 0x6e8,
1891 .security = 0x6ec,
1892 },
1893 },
1894 }, {
1895 .id = TEGRA194_MEMORY_CLIENT_PCIE3R,
1896 .name = "pcie3r",
1897 .sid = TEGRA194_SID_PCIE3,
1898 .regs = {
1899 .sid = {
1900 .override = 0x6f0,
1901 .security = 0x6f4,
1902 },
1903 },
1904 }, {
1905 .id = TEGRA194_MEMORY_CLIENT_PCIE3W,
1906 .name = "pcie3w",
1907 .sid = TEGRA194_SID_PCIE3,
1908 .regs = {
1909 .sid = {
1910 .override = 0x6f8,
1911 .security = 0x6fc,
1912 },
1913 },
1914 }, {
1915 .id = TEGRA194_MEMORY_CLIENT_PCIE4R,
1916 .name = "pcie4r",
1917 .sid = TEGRA194_SID_PCIE4,
1918 .regs = {
1919 .sid = {
1920 .override = 0x700,
1921 .security = 0x704,
1922 },
1923 },
1924 }, {
1925 .id = TEGRA194_MEMORY_CLIENT_PCIE4W,
1926 .name = "pcie4w",
1927 .sid = TEGRA194_SID_PCIE4,
1928 .regs = {
1929 .sid = {
1930 .override = 0x708,
1931 .security = 0x70c,
1932 },
1933 },
1934 }, {
1935 .id = TEGRA194_MEMORY_CLIENT_PCIE5R,
1936 .name = "pcie5r",
1937 .sid = TEGRA194_SID_PCIE5,
1938 .regs = {
1939 .sid = {
1940 .override = 0x710,
1941 .security = 0x714,
1942 },
1943 },
1944 }, {
1945 .id = TEGRA194_MEMORY_CLIENT_PCIE5W,
1946 .name = "pcie5w",
1947 .sid = TEGRA194_SID_PCIE5,
1948 .regs = {
1949 .sid = {
1950 .override = 0x718,
1951 .security = 0x71c,
1952 },
1953 },
1954 }, {
1955 .id = TEGRA194_MEMORY_CLIENT_ISPFALW,
1956 .name = "ispfalw",
1957 .sid = TEGRA194_SID_ISP_FALCON,
1958 .regs = {
1959 .sid = {
1960 .override = 0x720,
1961 .security = 0x724,
1962 },
1963 },
1964 }, {
1965 .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1,
1966 .name = "dla0rda1",
1967 .sid = TEGRA194_SID_NVDLA0,
1968 .regs = {
1969 .sid = {
1970 .override = 0x748,
1971 .security = 0x74c,
1972 },
1973 },
1974 }, {
1975 .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1,
1976 .name = "dla1rda1",
1977 .sid = TEGRA194_SID_NVDLA1,
1978 .regs = {
1979 .sid = {
1980 .override = 0x750,
1981 .security = 0x754,
1982 },
1983 },
1984 }, {
1985 .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1,
1986 .name = "pva0rda1",
1987 .sid = TEGRA194_SID_PVA0,
1988 .regs = {
1989 .sid = {
1990 .override = 0x758,
1991 .security = 0x75c,
1992 },
1993 },
1994 }, {
1995 .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1,
1996 .name = "pva0rdb1",
1997 .sid = TEGRA194_SID_PVA0,
1998 .regs = {
1999 .sid = {
2000 .override = 0x760,
2001 .security = 0x764,
2002 },
2003 },
2004 }, {
2005 .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1,
2006 .name = "pva1rda1",
2007 .sid = TEGRA194_SID_PVA1,
2008 .regs = {
2009 .sid = {
2010 .override = 0x768,
2011 .security = 0x76c,
2012 },
2013 },
2014 }, {
2015 .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1,
2016 .name = "pva1rdb1",
2017 .sid = TEGRA194_SID_PVA1,
2018 .regs = {
2019 .sid = {
2020 .override = 0x770,
2021 .security = 0x774,
2022 },
2023 },
2024 }, {
2025 .id = TEGRA194_MEMORY_CLIENT_PCIE5R1,
2026 .name = "pcie5r1",
2027 .sid = TEGRA194_SID_PCIE5,
2028 .regs = {
2029 .sid = {
2030 .override = 0x778,
2031 .security = 0x77c,
2032 },
2033 },
2034 }, {
2035 .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1,
2036 .name = "nvencsrd1",
2037 .sid = TEGRA194_SID_NVENC,
2038 .regs = {
2039 .sid = {
2040 .override = 0x780,
2041 .security = 0x784,
2042 },
2043 },
2044 }, {
2045 .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1,
2046 .name = "nvenc1srd1",
2047 .sid = TEGRA194_SID_NVENC1,
2048 .regs = {
2049 .sid = {
2050 .override = 0x788,
2051 .security = 0x78c,
2052 },
2053 },
2054 }, {
2055 .id = TEGRA194_MEMORY_CLIENT_ISPRA1,
2056 .name = "ispra1",
2057 .sid = TEGRA194_SID_ISP,
2058 .regs = {
2059 .sid = {
2060 .override = 0x790,
2061 .security = 0x794,
2062 },
2063 },
2064 }, {
2065 .id = TEGRA194_MEMORY_CLIENT_PCIE0R1,
2066 .name = "pcie0r1",
2067 .sid = TEGRA194_SID_PCIE0,
2068 .regs = {
2069 .sid = {
2070 .override = 0x798,
2071 .security = 0x79c,
2072 },
2073 },
2074 }, {
2075 .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD,
2076 .name = "nvdec1srd",
2077 .sid = TEGRA194_SID_NVDEC1,
2078 .regs = {
2079 .sid = {
2080 .override = 0x7c8,
2081 .security = 0x7cc,
2082 },
2083 },
2084 }, {
2085 .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1,
2086 .name = "nvdec1srd1",
2087 .sid = TEGRA194_SID_NVDEC1,
2088 .regs = {
2089 .sid = {
2090 .override = 0x7d0,
2091 .security = 0x7d4,
2092 },
2093 },
2094 }, {
2095 .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR,
2096 .name = "nvdec1swr",
2097 .sid = TEGRA194_SID_NVDEC1,
2098 .regs = {
2099 .sid = {
2100 .override = 0x7d8,
2101 .security = 0x7dc,
2102 },
2103 },
2104 }, {
2105 .id = TEGRA194_MEMORY_CLIENT_MIU5R,
2106 .name = "miu5r",
2107 .sid = TEGRA194_SID_MIU,
2108 .regs = {
2109 .sid = {
2110 .override = 0x7e0,
2111 .security = 0x7e4,
2112 },
2113 },
2114 }, {
2115 .id = TEGRA194_MEMORY_CLIENT_MIU5W,
2116 .name = "miu5w",
2117 .sid = TEGRA194_SID_MIU,
2118 .regs = {
2119 .sid = {
2120 .override = 0x7e8,
2121 .security = 0x7ec,
2122 },
2123 },
2124 }, {
2125 .id = TEGRA194_MEMORY_CLIENT_MIU6R,
2126 .name = "miu6r",
2127 .sid = TEGRA194_SID_MIU,
2128 .regs = {
2129 .sid = {
2130 .override = 0x7f0,
2131 .security = 0x7f4,
2132 },
2133 },
2134 }, {
2135 .id = TEGRA194_MEMORY_CLIENT_MIU6W,
2136 .name = "miu6w",
2137 .sid = TEGRA194_SID_MIU,
2138 .regs = {
2139 .sid = {
2140 .override = 0x7f8,
2141 .security = 0x7fc,
2142 },
2143 },
2144 },
2145};
2146
2147const struct tegra_mc_soc tegra194_mc_soc = {
2148 .num_clients = ARRAY_SIZE(tegra194_mc_clients),
2149 .clients = tegra194_mc_clients,
2150 .num_address_bits = 40,
2151 .ops = &tegra186_mc_ops,
2152};
2153#endif