mc.c (1c74d5c0de0c2cc29fef97a19251da2ad6f579bd) mc.c (a8d502fd33484ed8c4acc6acae73918844ca6811)
1/*
2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

--- 23 unchanged lines hidden (view full) ---

32#define MC_ERR_STATUS_NONSECURE (1 << 25)
33#define MC_ERR_STATUS_ADR_HI_SHIFT 20
34#define MC_ERR_STATUS_ADR_HI_MASK 0x3
35#define MC_ERR_STATUS_SECURITY (1 << 17)
36#define MC_ERR_STATUS_RW (1 << 16)
37
38#define MC_ERR_ADR 0x0c
39
1/*
2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

--- 23 unchanged lines hidden (view full) ---

32#define MC_ERR_STATUS_NONSECURE (1 << 25)
33#define MC_ERR_STATUS_ADR_HI_SHIFT 20
34#define MC_ERR_STATUS_ADR_HI_MASK 0x3
35#define MC_ERR_STATUS_SECURITY (1 << 17)
36#define MC_ERR_STATUS_RW (1 << 16)
37
38#define MC_ERR_ADR 0x0c
39
40#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
41#define MC_SECURITY_VIOLATION_STATUS 0x74
42
40#define MC_EMEM_ARB_CFG 0x90
41#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
42#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
43#define MC_EMEM_ARB_MISC0 0xd8
44
45#define MC_EMEM_ADR_CFG 0x54
46#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
47
48static const struct of_device_id tegra_mc_of_match[] = {
43#define MC_EMEM_ARB_CFG 0x90
44#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
45#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
46#define MC_EMEM_ARB_MISC0 0xd8
47
48#define MC_EMEM_ADR_CFG 0x54
49#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
50
51static const struct of_device_id tegra_mc_of_match[] = {
52#ifdef CONFIG_ARCH_TEGRA_2x_SOC
53 { .compatible = "nvidia,tegra20-mc", .data = &tegra20_mc_soc },
54#endif
49#ifdef CONFIG_ARCH_TEGRA_3x_SOC
50 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
51#endif
52#ifdef CONFIG_ARCH_TEGRA_114_SOC
53 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
54#endif
55#ifdef CONFIG_ARCH_TEGRA_124_SOC
56 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },

--- 159 unchanged lines hidden (view full) ---

216 ram_code);
217
218 return 0;
219}
220
221static const char *const status_names[32] = {
222 [ 1] = "External interrupt",
223 [ 6] = "EMEM address decode error",
55#ifdef CONFIG_ARCH_TEGRA_3x_SOC
56 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
57#endif
58#ifdef CONFIG_ARCH_TEGRA_114_SOC
59 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
60#endif
61#ifdef CONFIG_ARCH_TEGRA_124_SOC
62 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },

--- 159 unchanged lines hidden (view full) ---

222 ram_code);
223
224 return 0;
225}
226
227static const char *const status_names[32] = {
228 [ 1] = "External interrupt",
229 [ 6] = "EMEM address decode error",
230 [ 7] = "GART page fault",
224 [ 8] = "Security violation",
225 [ 9] = "EMEM arbitration error",
226 [10] = "Page fault",
227 [11] = "Invalid APB ASID update",
228 [12] = "VPR violation",
229 [13] = "Secure carveout violation",
230 [16] = "MTS carveout violation",
231};

--- 97 unchanged lines hidden (view full) ---

329 }
330
331 /* clear interrupts */
332 mc_writel(mc, status, MC_INTSTATUS);
333
334 return IRQ_HANDLED;
335}
336
231 [ 8] = "Security violation",
232 [ 9] = "EMEM arbitration error",
233 [10] = "Page fault",
234 [11] = "Invalid APB ASID update",
235 [12] = "VPR violation",
236 [13] = "Secure carveout violation",
237 [16] = "MTS carveout violation",
238};

--- 97 unchanged lines hidden (view full) ---

336 }
337
338 /* clear interrupts */
339 mc_writel(mc, status, MC_INTSTATUS);
340
341 return IRQ_HANDLED;
342}
343
344static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
345{
346 struct tegra_mc *mc = data;
347 unsigned long status;
348 unsigned int bit;
349
350 /* mask all interrupts to avoid flooding */
351 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
352 if (!status)
353 return IRQ_NONE;
354
355 for_each_set_bit(bit, &status, 32) {
356 const char *direction = "read", *secure = "";
357 const char *error = status_names[bit];
358 const char *client, *desc;
359 phys_addr_t addr;
360 u32 value, reg;
361 u8 id, type;
362
363 switch (BIT(bit)) {
364 case MC_INT_DECERR_EMEM:
365 reg = MC_DECERR_EMEM_OTHERS_STATUS;
366 value = mc_readl(mc, reg);
367
368 id = value & mc->soc->client_id_mask;
369 desc = error_names[2];
370
371 if (value & BIT(31))
372 direction = "write";
373 break;
374
375 case MC_INT_INVALID_GART_PAGE:
376 dev_err_ratelimited(mc->dev, "%s\n", error);
377 continue;
378
379 case MC_INT_SECURITY_VIOLATION:
380 reg = MC_SECURITY_VIOLATION_STATUS;
381 value = mc_readl(mc, reg);
382
383 id = value & mc->soc->client_id_mask;
384 type = (value & BIT(30)) ? 4 : 3;
385 desc = error_names[type];
386 secure = "secure ";
387
388 if (value & BIT(31))
389 direction = "write";
390 break;
391
392 default:
393 continue;
394 }
395
396 client = mc->soc->clients[id].name;
397 addr = mc_readl(mc, reg + sizeof(u32));
398
399 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
400 client, secure, direction, &addr, error,
401 desc);
402 }
403
404 /* clear interrupts */
405 mc_writel(mc, status, MC_INTSTATUS);
406
407 return IRQ_HANDLED;
408}
409
337static int tegra_mc_probe(struct platform_device *pdev)
338{
339 const struct of_device_id *match;
340 struct resource *res;
341 struct tegra_mc *mc;
410static int tegra_mc_probe(struct platform_device *pdev)
411{
412 const struct of_device_id *match;
413 struct resource *res;
414 struct tegra_mc *mc;
415 void *isr;
342 int err;
343
344 match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
345 if (!match)
346 return -ENODEV;
347
348 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
349 if (!mc)

--- 6 unchanged lines hidden (view full) ---

356 /* length of MC tick in nanoseconds */
357 mc->tick = 30;
358
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 mc->regs = devm_ioremap_resource(&pdev->dev, res);
361 if (IS_ERR(mc->regs))
362 return PTR_ERR(mc->regs);
363
416 int err;
417
418 match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
419 if (!match)
420 return -ENODEV;
421
422 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
423 if (!mc)

--- 6 unchanged lines hidden (view full) ---

430 /* length of MC tick in nanoseconds */
431 mc->tick = 30;
432
433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
434 mc->regs = devm_ioremap_resource(&pdev->dev, res);
435 if (IS_ERR(mc->regs))
436 return PTR_ERR(mc->regs);
437
364 mc->clk = devm_clk_get(&pdev->dev, "mc");
365 if (IS_ERR(mc->clk)) {
366 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
367 PTR_ERR(mc->clk));
368 return PTR_ERR(mc->clk);
369 }
438#ifdef CONFIG_ARCH_TEGRA_2x_SOC
439 if (mc->soc == &tegra20_mc_soc) {
440 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
441 mc->regs2 = devm_ioremap_resource(&pdev->dev, res);
442 if (IS_ERR(mc->regs2))
443 return PTR_ERR(mc->regs2);
370
444
371 err = tegra_mc_setup_latency_allowance(mc);
372 if (err < 0) {
373 dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
374 err);
375 return err;
445 isr = tegra20_mc_irq;
446 } else
447#endif
448 {
449 mc->clk = devm_clk_get(&pdev->dev, "mc");
450 if (IS_ERR(mc->clk)) {
451 dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
452 PTR_ERR(mc->clk));
453 return PTR_ERR(mc->clk);
454 }
455
456 err = tegra_mc_setup_latency_allowance(mc);
457 if (err < 0) {
458 dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
459 err);
460 return err;
461 }
462
463 isr = tegra_mc_irq;
376 }
377
378 err = tegra_mc_setup_timings(mc);
379 if (err < 0) {
380 dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
381 return err;
382 }
383

--- 11 unchanged lines hidden (view full) ---

395 dev_err(&pdev->dev, "interrupt not specified\n");
396 return mc->irq;
397 }
398
399 WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
400
401 mc_writel(mc, mc->soc->intmask, MC_INTMASK);
402
464 }
465
466 err = tegra_mc_setup_timings(mc);
467 if (err < 0) {
468 dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
469 return err;
470 }
471

--- 11 unchanged lines hidden (view full) ---

483 dev_err(&pdev->dev, "interrupt not specified\n");
484 return mc->irq;
485 }
486
487 WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n");
488
489 mc_writel(mc, mc->soc->intmask, MC_INTMASK);
490
403 err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED,
491 err = devm_request_irq(&pdev->dev, mc->irq, isr, IRQF_SHARED,
404 dev_name(&pdev->dev), mc);
405 if (err < 0) {
406 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
407 err);
408 return err;
409 }
410
411 return 0;

--- 21 unchanged lines hidden --- 		492 dev_name(&pdev->dev), mc);
493 if (err < 0) {
494 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
495 err);
496 return err;
497 }
498
499 return 0;

--- 21 unchanged lines hidden ---