qm1d1c0042.c (e5451c8f8330e03ad3cfa16048b4daf961af434f) qm1d1c0042.c (ab4d14528fdf946dfa7177b53e64f78bf8cce03a)
1/*
2 * Sharp QM1D1C0042 8PSK tuner driver
3 *
4 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.

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27 * Thus some part of the code might be dependent on PT3 specific config.
28 */
29
30#include <linux/kernel.h>
31#include <linux/math64.h>
32#include "qm1d1c0042.h"
33
34#define QM1D1C0042_NUM_REGS 0x20
1/*
2 * Sharp QM1D1C0042 8PSK tuner driver
3 *
4 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.

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27 * Thus some part of the code might be dependent on PT3 specific config.
28 */
29
30#include <linux/kernel.h>
31#include <linux/math64.h>
32#include "qm1d1c0042.h"
33
34#define QM1D1C0042_NUM_REGS 0x20
35#define QM1D1C0042_NUM_REG_ROWS 2
35
36
36static const u8 reg_initval[QM1D1C0042_NUM_REGS] = {
37 0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
38 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
39 0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
40 0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
37static const u8
38reg_initval[QM1D1C0042_NUM_REG_ROWS][QM1D1C0042_NUM_REGS] = { {
39 0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33,
40 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
41 0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86,
42 0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00
43 }, {
44 0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33,
45 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
46 0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6,
47 0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00
48 }
41};
42
49};
50
51static int reg_index;
52
43static const struct qm1d1c0042_config default_cfg = {
44 .xtal_freq = 16000,
45 .lpf = 1,
46 .fast_srch = 0,
47 .lpf_wait = 20,
48 .fast_srch_wait = 4,
49 .normal_srch_wait = 15,
50};

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315
316static int qm1d1c0042_init(struct dvb_frontend *fe)
317{
318 struct qm1d1c0042_state *state;
319 u8 val;
320 int i, ret;
321
322 state = fe->tuner_priv;
53static const struct qm1d1c0042_config default_cfg = {
54 .xtal_freq = 16000,
55 .lpf = 1,
56 .fast_srch = 0,
57 .lpf_wait = 20,
58 .fast_srch_wait = 4,
59 .normal_srch_wait = 15,
60};

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325
326static int qm1d1c0042_init(struct dvb_frontend *fe)
327{
328 struct qm1d1c0042_state *state;
329 u8 val;
330 int i, ret;
331
332 state = fe->tuner_priv;
323 memcpy(state->regs, reg_initval, sizeof(reg_initval));
324
325 reg_write(state, 0x01, 0x0c);
326 reg_write(state, 0x01, 0x0c);
327
328 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */
329 if (ret < 0)
330 goto failed;
331 usleep_range(2000, 3000);
332
333
334 reg_write(state, 0x01, 0x0c);
335 reg_write(state, 0x01, 0x0c);
336
337 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */
338 if (ret < 0)
339 goto failed;
340 usleep_range(2000, 3000);
341
333 val = state->regs[0x01] | 0x10;
334 ret = reg_write(state, 0x01, val); /* soft reset off */
342 ret = reg_write(state, 0x01, 0x1c); /* soft reset off */
335 if (ret < 0)
336 goto failed;
337
343 if (ret < 0)
344 goto failed;
345
338 /* check ID */
346 /* check ID and choose initial registers corresponding ID */
339 ret = reg_read(state, 0x00, &val);
347 ret = reg_read(state, 0x00, &val);
340 if (ret < 0 || val != 0x48)
348 if (ret < 0)
341 goto failed;
349 goto failed;
350 for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS;
351 reg_index++) {
352 if (val == reg_initval[reg_index][0x00])
353 break;
354 }
355 if (reg_index >= QM1D1C0042_NUM_REG_ROWS)
356 goto failed;
357 memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS);
342 usleep_range(2000, 3000);
343
344 state->regs[0x0c] |= 0x40;
345 ret = reg_write(state, 0x0c, state->regs[0x0c]);
346 if (ret < 0)
347 goto failed;
348 msleep(state->cfg.lpf_wait);
349

--- 99 unchanged lines hidden --- 		358 usleep_range(2000, 3000);
359
360 state->regs[0x0c] |= 0x40;
361 ret = reg_write(state, 0x0c, state->regs[0x0c]);
362 if (ret < 0)
363 goto failed;
364 msleep(state->cfg.lpf_wait);
365

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