zr36060.h (0337966d121ebebf73a1c346123e8112796e684e) zr36060.h (2a0c28063de23646bb56152095ce73ea2284dc26)
1/* SPDX-License-Identifier: GPL-2.0-or-later */
1/*
2 * Zoran ZR36060 basic configuration functions - header file
3 *
4 * Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be>
2/*
3 * Zoran ZR36060 basic configuration functions - header file
4 *
5 * Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be>
5 *
6 * $Id: zr36060.h,v 1.1.1.1.2.3 2003/01/14 21:18:47 rbultje Exp $
7 *
8 * ------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * ------------------------------------------------------------------------
21 */
22
23#ifndef ZR36060_H
24#define ZR36060_H
25
26#include "videocodec.h"
27
28/* data stored for each zoran jpeg codec chip */

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81#define ZR060_ACV_HI 0x016
82#define ZR060_ACV_MH 0x017
83#define ZR060_ACV_ML 0x018
84#define ZR060_ACV_LO 0x019
85#define ZR060_ACT_HI 0x01a
86#define ZR060_ACT_MH 0x01b
87#define ZR060_ACT_ML 0x01c
88#define ZR060_ACT_LO 0x01d
6 */
7
8#ifndef ZR36060_H
9#define ZR36060_H
10
11#include "videocodec.h"
12
13/* data stored for each zoran jpeg codec chip */

--- 52 unchanged lines hidden (view full) ---

66#define ZR060_ACV_HI 0x016
67#define ZR060_ACV_MH 0x017
68#define ZR060_ACV_ML 0x018
69#define ZR060_ACV_LO 0x019
70#define ZR060_ACT_HI 0x01a
71#define ZR060_ACT_MH 0x01b
72#define ZR060_ACT_ML 0x01c
73#define ZR060_ACT_LO 0x01d
89#define ZR060_ACV_TRUN_HI 0x01e
90#define ZR060_ACV_TRUN_MH 0x01f
91#define ZR060_ACV_TRUN_ML 0x020
92#define ZR060_ACV_TRUN_LO 0x021
74#define ZR060_ACV_TURN_HI 0x01e
75#define ZR060_ACV_TURN_MH 0x01f
76#define ZR060_ACV_TURN_ML 0x020
77#define ZR060_ACV_TURN_LO 0x021
93#define ZR060_IDR_DEV 0x022
94#define ZR060_IDR_REV 0x023
95#define ZR060_TCR_HI 0x024
96#define ZR060_TCR_LO 0x025
97#define ZR060_VCR 0x030
98#define ZR060_VPR 0x031
99#define ZR060_SR 0x032
100#define ZR060_BCR_Y 0x033

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134#define ZR060_DRI_IDX 0x0c0
135#define ZR060_DQT_IDX 0x0cc
136#define ZR060_DHT_IDX 0x1d4
137#define ZR060_APP_IDX 0x380
138#define ZR060_COM_IDX 0x3c0
139
140/* ZR36060 LOAD register bits */
141
78#define ZR060_IDR_DEV 0x022
79#define ZR060_IDR_REV 0x023
80#define ZR060_TCR_HI 0x024
81#define ZR060_TCR_LO 0x025
82#define ZR060_VCR 0x030
83#define ZR060_VPR 0x031
84#define ZR060_SR 0x032
85#define ZR060_BCR_Y 0x033

--- 33 unchanged lines hidden (view full) ---

119#define ZR060_DRI_IDX 0x0c0
120#define ZR060_DQT_IDX 0x0cc
121#define ZR060_DHT_IDX 0x1d4
122#define ZR060_APP_IDX 0x380
123#define ZR060_COM_IDX 0x3c0
124
125/* ZR36060 LOAD register bits */
126
142#define ZR060_LOAD_Load (1 << 7)
143#define ZR060_LOAD_SyncRst (1 << 0)
127#define ZR060_LOAD_LOAD BIT(7)
128#define ZR060_LOAD_SYNC_RST BIT(0)
144
145/* ZR36060 Code FIFO Status register bits */
146
129
130/* ZR36060 Code FIFO Status register bits */
131
147#define ZR060_CFSR_Busy (1 << 7)
148#define ZR060_CFSR_CBusy (1 << 2)
132#define ZR060_CFSR_BUSY BIT(7)
133#define ZR060_CFSR_C_BUSY BIT(2)
149#define ZR060_CFSR_CFIFO (3 << 0)
150
151/* ZR36060 Code Interface register */
152
134#define ZR060_CFSR_CFIFO (3 << 0)
135
136/* ZR36060 Code Interface register */
137
153#define ZR060_CIR_Code16 (1 << 7)
154#define ZR060_CIR_Endian (1 << 6)
155#define ZR060_CIR_CFIS (1 << 2)
156#define ZR060_CIR_CodeMstr (1 << 0)
138#define ZR060_CIR_CODE16 BIT(7)
139#define ZR060_CIR_ENDIAN BIT(6)
140#define ZR060_CIR_CFIS BIT(2)
141#define ZR060_CIR_CODE_MSTR BIT(0)
157
158/* ZR36060 Codec Mode register */
159
142
143/* ZR36060 Codec Mode register */
144
160#define ZR060_CMR_Comp (1 << 7)
161#define ZR060_CMR_ATP (1 << 6)
162#define ZR060_CMR_Pass2 (1 << 5)
163#define ZR060_CMR_TLM (1 << 4)
164#define ZR060_CMR_BRB (1 << 2)
165#define ZR060_CMR_FSF (1 << 1)
145#define ZR060_CMR_COMP BIT(7)
146#define ZR060_CMR_ATP BIT(6)
147#define ZR060_CMR_PASS2 BIT(5)
148#define ZR060_CMR_TLM BIT(4)
149#define ZR060_CMR_BRB BIT(2)
150#define ZR060_CMR_FSF BIT(1)
166
167/* ZR36060 Markers Enable register */
168
151
152/* ZR36060 Markers Enable register */
153
169#define ZR060_MER_App (1 << 7)
170#define ZR060_MER_Com (1 << 6)
171#define ZR060_MER_DRI (1 << 5)
172#define ZR060_MER_DQT (1 << 4)
173#define ZR060_MER_DHT (1 << 3)
154#define ZR060_MER_APP BIT(7)
155#define ZR060_MER_COM BIT(6)
156#define ZR060_MER_DRI BIT(5)
157#define ZR060_MER_DQT BIT(4)
158#define ZR060_MER_DHT BIT(3)
174
175/* ZR36060 Interrupt Mask register */
176
159
160/* ZR36060 Interrupt Mask register */
161
177#define ZR060_IMR_EOAV (1 << 3)
178#define ZR060_IMR_EOI (1 << 2)
179#define ZR060_IMR_End (1 << 1)
180#define ZR060_IMR_DataErr (1 << 0)
162#define ZR060_IMR_EOAV BIT(3)
163#define ZR060_IMR_EOI BIT(2)
164#define ZR060_IMR_END BIT(1)
165#define ZR060_IMR_DATA_ERR BIT(0)
181
182/* ZR36060 Interrupt Status register */
183
166
167/* ZR36060 Interrupt Status register */
168
184#define ZR060_ISR_ProCnt (3 << 6)
185#define ZR060_ISR_EOAV (1 << 3)
186#define ZR060_ISR_EOI (1 << 2)
187#define ZR060_ISR_End (1 << 1)
188#define ZR060_ISR_DataErr (1 << 0)
169#define ZR060_ISR_PRO_CNT (3 << 6)
170#define ZR060_ISR_EOAV BIT(3)
171#define ZR060_ISR_EOI BIT(2)
172#define ZR060_ISR_END BIT(1)
173#define ZR060_ISR_DATA_ERR BIT(0)
189
190/* ZR36060 Video Control register */
191
174
175/* ZR36060 Video Control register */
176
192#define ZR060_VCR_Video8 (1 << 7)
193#define ZR060_VCR_Range (1 << 6)
194#define ZR060_VCR_FIDet (1 << 3)
195#define ZR060_VCR_FIVedge (1 << 2)
196#define ZR060_VCR_FIExt (1 << 1)
197#define ZR060_VCR_SyncMstr (1 << 0)
177#define ZR060_VCR_VIDEO8 BIT(7)
178#define ZR060_VCR_RANGE BIT(6)
179#define ZR060_VCR_FI_DET BIT(3)
180#define ZR060_VCR_FI_VEDGE BIT(2)
181#define ZR060_VCR_FI_EXT BIT(1)
182#define ZR060_VCR_SYNC_MSTR BIT(0)
198
199/* ZR36060 Video Polarity register */
200
183
184/* ZR36060 Video Polarity register */
185
201#define ZR060_VPR_VCLKPol (1 << 7)
202#define ZR060_VPR_PValPol (1 << 6)
203#define ZR060_VPR_PoePol (1 << 5)
204#define ZR060_VPR_SImgPol (1 << 4)
205#define ZR060_VPR_BLPol (1 << 3)
206#define ZR060_VPR_FIPol (1 << 2)
207#define ZR060_VPR_HSPol (1 << 1)
208#define ZR060_VPR_VSPol (1 << 0)
186#define ZR060_VPR_VCLK_POL BIT(7)
187#define ZR060_VPR_P_VAL_POL BIT(6)
188#define ZR060_VPR_POE_POL BIT(5)
189#define ZR060_VPR_S_IMG_POL BIT(4)
190#define ZR060_VPR_BL_POL BIT(3)
191#define ZR060_VPR_FI_POL BIT(2)
192#define ZR060_VPR_HS_POL BIT(1)
193#define ZR060_VPR_VS_POL BIT(0)
209
210/* ZR36060 Scaling register */
211
194
195/* ZR36060 Scaling register */
196
212#define ZR060_SR_VScale (1 << 2)
213#define ZR060_SR_HScale2 (1 << 0)
214#define ZR060_SR_HScale4 (2 << 0)
197#define ZR060_SR_V_SCALE BIT(2)
198#define ZR060_SR_H_SCALE2 BIT(0)
199#define ZR060_SR_H_SCALE4 (2 << 0)
215
200
201int zr36060_init_module(void);
202void zr36060_cleanup_module(void);
216#endif /*fndef ZR36060_H */
203#endif /*fndef ZR36060_H */