tw68-risc.c (5740f4e75f713015067e2667a52bd3b35ef91e07) tw68-risc.c (e15d1c12c5878b3a80d6573af1721e17264e0286)
1/*
2 * tw68_risc.c
3 * Part of the device driver for Techwell 68xx based cards
4 *
5 * Much of this code is derived from the cx88 and sa7134 drivers, which
6 * were in turn derived from the bt87x driver. The original work was by
7 * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
8 * Hans Verkuil, Andy Walls and many others. Their work is gratefully
9 * acknowledged. Full credit goes to them - any problems within this code
10 * are mine.
11 *
1/*
2 * tw68_risc.c
3 * Part of the device driver for Techwell 68xx based cards
4 *
5 * Much of this code is derived from the cx88 and sa7134 drivers, which
6 * were in turn derived from the bt87x driver. The original work was by
7 * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
8 * Hans Verkuil, Andy Walls and many others. Their work is gratefully
9 * acknowledged. Full credit goes to them - any problems within this code
10 * are mine.
11 *
12 * Copyright (C) 2009 William M. Brack <wbrack@mmm.com.hk>
12 * Copyright (C) 2009 William M. Brack
13 *
13 *
14 * Refactored and updated to the latest v4l core frameworks:
15 *
16 * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
17 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
27 */
28
29#include "tw68.h"
30
27 */
28
29#include "tw68.h"
30
31#define NO_SYNC_LINE (-1U)
32
33/**
34 * @rp pointer to current risc program position
35 * @sglist pointer to "scatter-gather list" of buffer pointers
36 * @offset offset to target memory buffer
37 * @sync_line 0 -> no sync, 1 -> odd sync, 2 -> even sync
38 * @bpl number of bytes per scan line
39 * @padding number of bytes of padding to add
40 * @lines number of lines in field
31/**
32 * @rp pointer to current risc program position
33 * @sglist pointer to "scatter-gather list" of buffer pointers
34 * @offset offset to target memory buffer
35 * @sync_line 0 -> no sync, 1 -> odd sync, 2 -> even sync
36 * @bpl number of bytes per scan line
37 * @padding number of bytes of padding to add
38 * @lines number of lines in field
41 * @lpi lines per IRQ, or 0 to not generate irqs
42 * Note: IRQ to be generated _after_ lpi lines are transferred
39 * @jump insert a jump at the start
43 */
44static __le32 *tw68_risc_field(__le32 *rp, struct scatterlist *sglist,
45 unsigned int offset, u32 sync_line,
46 unsigned int bpl, unsigned int padding,
40 */
41static __le32 *tw68_risc_field(__le32 *rp, struct scatterlist *sglist,
42 unsigned int offset, u32 sync_line,
43 unsigned int bpl, unsigned int padding,
47 unsigned int lines, unsigned int lpi)
44 unsigned int lines, bool jump)
48{
49 struct scatterlist *sg;
50 unsigned int line, todo, done;
51
45{
46 struct scatterlist *sg;
47 unsigned int line, todo, done;
48
52 /* sync instruction */
53 if (sync_line != NO_SYNC_LINE) {
54 if (sync_line == 1)
55 *(rp++) = cpu_to_le32(RISC_SYNCO);
56 else
57 *(rp++) = cpu_to_le32(RISC_SYNCE);
49 if (jump) {
50 *(rp++) = cpu_to_le32(RISC_JUMP);
58 *(rp++) = 0;
59 }
51 *(rp++) = 0;
52 }
53
54 /* sync instruction */
55 if (sync_line == 1)
56 *(rp++) = cpu_to_le32(RISC_SYNCO);
57 else
58 *(rp++) = cpu_to_le32(RISC_SYNCE);
59 *(rp++) = 0;
60
60 /* scan lines */
61 sg = sglist;
62 for (line = 0; line < lines; line++) {
63 /* calculate next starting position */
64 while (offset && offset >= sg_dma_len(sg)) {
65 offset -= sg_dma_len(sg);
61 /* scan lines */
62 sg = sglist;
63 for (line = 0; line < lines; line++) {
64 /* calculate next starting position */
65 while (offset && offset >= sg_dma_len(sg)) {
66 offset -= sg_dma_len(sg);
66 sg++;
67 sg = sg_next(sg);
67 }
68 if (bpl <= sg_dma_len(sg) - offset) {
69 /* fits into current chunk */
70 *(rp++) = cpu_to_le32(RISC_LINESTART |
71 /* (offset<<12) |*/ bpl);
72 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
73 offset += bpl;
74 } else {

--- 6 unchanged lines hidden (view full) ---

81 todo = bpl; /* one full line to be done */
82 /* first fragment */
83 done = (sg_dma_len(sg) - offset);
84 *(rp++) = cpu_to_le32(RISC_LINESTART |
85 (7 << 24) |
86 done);
87 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
88 todo -= done;
68 }
69 if (bpl <= sg_dma_len(sg) - offset) {
70 /* fits into current chunk */
71 *(rp++) = cpu_to_le32(RISC_LINESTART |
72 /* (offset<<12) |*/ bpl);
73 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
74 offset += bpl;
75 } else {

--- 6 unchanged lines hidden (view full) ---

82 todo = bpl; /* one full line to be done */
83 /* first fragment */
84 done = (sg_dma_len(sg) - offset);
85 *(rp++) = cpu_to_le32(RISC_LINESTART |
86 (7 << 24) |
87 done);
88 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
89 todo -= done;
89 sg++;
90 sg = sg_next(sg);
90 /* succeeding fragments have no offset */
91 while (todo > sg_dma_len(sg)) {
92 *(rp++) = cpu_to_le32(RISC_INLINE |
93 (done << 12) |
94 sg_dma_len(sg));
95 *(rp++) = cpu_to_le32(sg_dma_address(sg));
96 todo -= sg_dma_len(sg);
91 /* succeeding fragments have no offset */
92 while (todo > sg_dma_len(sg)) {
93 *(rp++) = cpu_to_le32(RISC_INLINE |
94 (done << 12) |
95 sg_dma_len(sg));
96 *(rp++) = cpu_to_le32(sg_dma_address(sg));
97 todo -= sg_dma_len(sg);
97 sg++;
98 sg = sg_next(sg);
98 done += sg_dma_len(sg);
99 }
100 if (todo) {
101 /* final chunk - offset 0, count 'todo' */
102 *(rp++) = cpu_to_le32(RISC_INLINE |
103 (done << 12) |
104 todo);
105 *(rp++) = cpu_to_le32(sg_dma_address(sg));
106 }
107 offset = todo;
108 }
109 offset += padding;
99 done += sg_dma_len(sg);
100 }
101 if (todo) {
102 /* final chunk - offset 0, count 'todo' */
103 *(rp++) = cpu_to_le32(RISC_INLINE |
104 (done << 12) |
105 todo);
106 *(rp++) = cpu_to_le32(sg_dma_address(sg));
107 }
108 offset = todo;
109 }
110 offset += padding;
110 /* If this line needs an interrupt, put it in */
111 if (lpi && line > 0 && !(line % lpi))
112 *(rp-2) |= RISC_INT_BIT;
113 }
114
115 return rp;
116}
117
118/**
119 * tw68_risc_buffer
120 *
111 }
112
113 return rp;
114}
115
116/**
117 * tw68_risc_buffer
118 *
121 * This routine is called by tw68-video. It allocates
122 * memory for the dma controller "program" and then fills in that
123 * memory with the appropriate "instructions".
119 * This routine is called by tw68-video. It allocates
120 * memory for the dma controller "program" and then fills in that
121 * memory with the appropriate "instructions".
124 *
122 *
125 * @pci_dev structure with info about the pci
126 * slot which our device is in.
127 * @risc structure with info about the memory
128 * used for our controller program.
129 * @sglist scatter-gather list entry
130 * @top_offset offset within the risc program area for the
131 * first odd frame line
132 * @bottom_offset offset within the risc program area for the
133 * first even frame line
134 * @bpl number of data bytes per scan line
135 * @padding number of extra bytes to add at end of line
136 * @lines number of scan lines
123 * @pci_dev structure with info about the pci
124 * slot which our device is in.
125 * @risc structure with info about the memory
126 * used for our controller program.
127 * @sglist scatter-gather list entry
128 * @top_offset offset within the risc program area for the
129 * first odd frame line
130 * @bottom_offset offset within the risc program area for the
131 * first even frame line
132 * @bpl number of data bytes per scan line
133 * @padding number of extra bytes to add at end of line
134 * @lines number of scan lines
137 */
138int tw68_risc_buffer(struct pci_dev *pci,
135 */
136int tw68_risc_buffer(struct pci_dev *pci,
139 struct btcx_riscmem *risc,
137 struct tw68_buf *buf,
140 struct scatterlist *sglist,
141 unsigned int top_offset,
142 unsigned int bottom_offset,
143 unsigned int bpl,
144 unsigned int padding,
145 unsigned int lines)
146{
147 u32 instructions, fields;
148 __le32 *rp;
138 struct scatterlist *sglist,
139 unsigned int top_offset,
140 unsigned int bottom_offset,
141 unsigned int bpl,
142 unsigned int padding,
143 unsigned int lines)
144{
145 u32 instructions, fields;
146 __le32 *rp;
149 int rc;
150
151 fields = 0;
152 if (UNSET != top_offset)
153 fields++;
154 if (UNSET != bottom_offset)
155 fields++;
156 /*
157 * estimate risc mem: worst case is one write per page border +
147
148 fields = 0;
149 if (UNSET != top_offset)
150 fields++;
151 if (UNSET != bottom_offset)
152 fields++;
153 /*
154 * estimate risc mem: worst case is one write per page border +
158 * one write per scan line + syncs + jump (all 2 dwords).
155 * one write per scan line + syncs + 2 jumps (all 2 dwords).
159 * Padding can cause next bpl to start close to a page border.
160 * First DMA region may be smaller than PAGE_SIZE
161 */
162 instructions = fields * (1 + (((bpl + padding) * lines) /
156 * Padding can cause next bpl to start close to a page border.
157 * First DMA region may be smaller than PAGE_SIZE
158 */
159 instructions = fields * (1 + (((bpl + padding) * lines) /
163 PAGE_SIZE) + lines) + 2;
164 rc = btcx_riscmem_alloc(pci, risc, instructions * 8);
165 if (rc < 0)
166 return rc;
160 PAGE_SIZE) + lines) + 4;
161 buf->size = instructions * 8;
162 buf->cpu = pci_alloc_consistent(pci, buf->size, &buf->dma);
163 if (buf->cpu == NULL)
164 return -ENOMEM;
167
168 /* write risc instructions */
165
166 /* write risc instructions */
169 rp = risc->cpu;
167 rp = buf->cpu;
170 if (UNSET != top_offset) /* generates SYNCO */
171 rp = tw68_risc_field(rp, sglist, top_offset, 1,
168 if (UNSET != top_offset) /* generates SYNCO */
169 rp = tw68_risc_field(rp, sglist, top_offset, 1,
172 bpl, padding, lines, 0);
170 bpl, padding, lines, true);
173 if (UNSET != bottom_offset) /* generates SYNCE */
174 rp = tw68_risc_field(rp, sglist, bottom_offset, 2,
171 if (UNSET != bottom_offset) /* generates SYNCE */
172 rp = tw68_risc_field(rp, sglist, bottom_offset, 2,
175 bpl, padding, lines, 0);
173 bpl, padding, lines, top_offset == UNSET);
176
177 /* save pointer to jmp instruction address */
174
175 /* save pointer to jmp instruction address */
178 risc->jmp = rp;
176 buf->jmp = rp;
177 buf->cpu[1] = cpu_to_le32(buf->dma + 8);
179 /* assure risc buffer hasn't overflowed */
178 /* assure risc buffer hasn't overflowed */
180 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
179 BUG_ON((buf->jmp - buf->cpu + 2) * sizeof(buf->cpu[0]) > buf->size);
181 return 0;
182}
183
184#if 0
185/* ------------------------------------------------------------------ */
186/* debug helper code */
187
188static void tw68_risc_decode(u32 risc, u32 addr)

--- 10 unchanged lines hidden (view full) ---

199 [RISC_OP(RISC_JUMP)] = {"jump", 0, 0, 1},
200 [RISC_OP(RISC_LINESTART)] = {"lineStart", 1, 1, 1},
201 [RISC_OP(RISC_INLINE)] = {"inline", 1, 1, 1},
202 };
203 u32 p;
204
205 p = RISC_OP(risc);
206 if (!(risc & 0x80000000) || !instr[p].name) {
180 return 0;
181}
182
183#if 0
184/* ------------------------------------------------------------------ */
185/* debug helper code */
186
187static void tw68_risc_decode(u32 risc, u32 addr)

--- 10 unchanged lines hidden (view full) ---

198 [RISC_OP(RISC_JUMP)] = {"jump", 0, 0, 1},
199 [RISC_OP(RISC_LINESTART)] = {"lineStart", 1, 1, 1},
200 [RISC_OP(RISC_INLINE)] = {"inline", 1, 1, 1},
201 };
202 u32 p;
203
204 p = RISC_OP(risc);
205 if (!(risc & 0x80000000) || !instr[p].name) {
207 printk(KERN_DEBUG "0x%08x [ INVALID ]\n", risc);
206 pr_debug("0x%08x [ INVALID ]\n", risc);
208 return;
209 }
207 return;
208 }
210 printk(KERN_DEBUG "0x%08x %-9s IRQ=%d",
209 pr_debug("0x%08x %-9s IRQ=%d",
211 risc, instr[p].name, (risc >> 27) & 1);
212 if (instr[p].has_data_type)
210 risc, instr[p].name, (risc >> 27) & 1);
211 if (instr[p].has_data_type)
213 printk(KERN_DEBUG " Type=%d", (risc >> 24) & 7);
212 pr_debug(" Type=%d", (risc >> 24) & 7);
214 if (instr[p].has_byte_info)
213 if (instr[p].has_byte_info)
215 printk(KERN_DEBUG " Start=0x%03x Count=%03u",
214 pr_debug(" Start=0x%03x Count=%03u",
216 (risc >> 12) & 0xfff, risc & 0xfff);
217 if (instr[p].has_addr)
215 (risc >> 12) & 0xfff, risc & 0xfff);
216 if (instr[p].has_addr)
218 printk(KERN_DEBUG " StartAddr=0x%08x", addr);
219 printk(KERN_DEBUG "\n");
217 pr_debug(" StartAddr=0x%08x", addr);
218 pr_debug("\n");
220}
221
219}
220
222void tw68_risc_program_dump(struct tw68_core *core,
223 struct btcx_riscmem *risc)
221void tw68_risc_program_dump(struct tw68_core *core, struct tw68_buf *buf)
224{
222{
225 __le32 *addr;
223 const __le32 *addr;
226
224
227 printk(KERN_DEBUG "%s: risc_program_dump: risc=%p, "
228 "risc->cpu=0x%p, risc->jmp=0x%p\n",
229 core->name, risc, risc->cpu, risc->jmp);
230 for (addr = risc->cpu; addr <= risc->jmp; addr += 2)
225 pr_debug("%s: risc_program_dump: risc=%p, buf->cpu=0x%p, buf->jmp=0x%p\n",
226 core->name, buf, buf->cpu, buf->jmp);
227 for (addr = buf->cpu; addr <= buf->jmp; addr += 2)
231 tw68_risc_decode(*addr, *(addr+1));
232}
228 tw68_risc_decode(*addr, *(addr+1));
229}
233EXPORT_SYMBOL_GPL(tw68_risc_program_dump);
234#endif
230#endif
235
236/*
237 * tw68_risc_stopper
238 * Normally, the risc code generated for a buffer ends with a
239 * JUMP instruction to direct the DMAP processor to the code for
240 * the next buffer. However, when there is no additional buffer
241 * currently available, the code instead jumps to this routine.
242 *
243 * My first try for a "stopper" program was just a simple
244 * "jump to self" instruction. Unfortunately, this caused the
245 * video FIFO to overflow. My next attempt was to just disable
246 * the DMAP processor. Unfortunately, this caused the video
247 * decoder to lose its synchronization. The solution to this was to
248 * add a "Sync-Odd" instruction, which "eats" all the video data
249 * until the start of the next odd field.
250 */
251int tw68_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc)
252{
253 __le32 *rp;
254 int rc;
255
256 rc = btcx_riscmem_alloc(pci, risc, 8*4);
257 if (rc < 0)
258 return rc;
259
260 /* write risc inststructions */
261 rp = risc->cpu;
262 *(rp++) = cpu_to_le32(RISC_SYNCO);
263 *(rp++) = 0;
264 *(rp++) = cpu_to_le32(RISC_JUMP);
265 *(rp++) = cpu_to_le32(risc->dma);
266 risc->jmp = risc->cpu;
267 return 0;
268}