| cx88-reg.h (7b61ba8ff838dbee422d428fbd882ab83db4b2d9) | cx88-reg.h (399426cadf5b0539a5b2a4d805257ce8acc6aba2) |
|---|---|
| 1/* | 1/* |
| 2 * cx88x-hw.h - CX2388x register offsets 3 * 4 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de) 5 * 2001 Michael Eskin 6 * 2002 Yurij Sysoev <yurij@naturesoft.net> 7 * 2003 Gerd Knorr <kraxel@bytesex.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ |
|
| 2 | 19 |
| 3 cx88x-hw.h - CX2388x register offsets 4 5 Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de) 6 2001 Michael Eskin 7 2002 Yurij Sysoev <yurij@naturesoft.net> 8 2003 Gerd Knorr <kraxel@bytesex.org> 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23*/ 24 | |
| 25#ifndef _CX88_REG_H_ 26#define _CX88_REG_H_ 27 | 20#ifndef _CX88_REG_H_ 21#define _CX88_REG_H_ 22 |
| 28/* ---------------------------------------------------------------------- */ 29/* PCI IDs and config space */ | 23/* 24 * PCI IDs and config space 25 */ |
| 30 31#ifndef PCI_VENDOR_ID_CONEXANT 32# define PCI_VENDOR_ID_CONEXANT 0x14F1 33#endif 34#ifndef PCI_DEVICE_ID_CX2300_VID 35# define PCI_DEVICE_ID_CX2300_VID 0x8800 36#endif 37 38#define CX88X_DEVCTRL 0x40 39#define CX88X_EN_TBFX 0x02 40#define CX88X_EN_VSFX 0x04 41 | 26 27#ifndef PCI_VENDOR_ID_CONEXANT 28# define PCI_VENDOR_ID_CONEXANT 0x14F1 29#endif 30#ifndef PCI_DEVICE_ID_CX2300_VID 31# define PCI_DEVICE_ID_CX2300_VID 0x8800 32#endif 33 34#define CX88X_DEVCTRL 0x40 35#define CX88X_EN_TBFX 0x02 36#define CX88X_EN_VSFX 0x04 37 |
| 42/* ---------------------------------------------------------------------- */ 43/* PCI controller registers */ | 38/* 39 * PCI controller registers 40 */ |
| 44 45/* Command and Status Register */ 46#define F0_CMD_STAT_MM 0x2f0004 47#define F1_CMD_STAT_MM 0x2f0104 48#define F2_CMD_STAT_MM 0x2f0204 49#define F3_CMD_STAT_MM 0x2f0304 50#define F4_CMD_STAT_MM 0x2f0404 51 --- 6 unchanged lines hidden (view full) --- 58 59/* Device Control #1 */ 60#define F0_BAR0_MM 0x2f0010 61#define F1_BAR0_MM 0x2f0110 62#define F2_BAR0_MM 0x2f0210 63#define F3_BAR0_MM 0x2f0310 64#define F4_BAR0_MM 0x2f0410 65 | 41 42/* Command and Status Register */ 43#define F0_CMD_STAT_MM 0x2f0004 44#define F1_CMD_STAT_MM 0x2f0104 45#define F2_CMD_STAT_MM 0x2f0204 46#define F3_CMD_STAT_MM 0x2f0304 47#define F4_CMD_STAT_MM 0x2f0404 48 --- 6 unchanged lines hidden (view full) --- 55 56/* Device Control #1 */ 57#define F0_BAR0_MM 0x2f0010 58#define F1_BAR0_MM 0x2f0110 59#define F2_BAR0_MM 0x2f0210 60#define F3_BAR0_MM 0x2f0310 61#define F4_BAR0_MM 0x2f0410 62 |
| 66/* ---------------------------------------------------------------------- */ 67/* DMA Controller registers */ | 63/* 64 * DMA Controller registers 65 */ |
| 68 69#define MO_PDMA_STHRSH 0x200000 // Source threshold 70#define MO_PDMA_STADRS 0x200004 // Source target address 71#define MO_PDMA_SIADRS 0x200008 // Source internal address 72#define MO_PDMA_SCNTRL 0x20000C // Source control 73#define MO_PDMA_DTHRSH 0x200010 // Destination threshold 74#define MO_PDMA_DTADRS 0x200014 // Destination target address 75#define MO_PDMA_DIADRS 0x200018 // Destination internal address --- 76 unchanged lines hidden (view full) --- 152#define MO_DMA26_CNT2 0x300154 // {11}RW* DMA Table Size : Ch#26 153#define MO_DMA27_CNT2 0x300158 // {11}RW* DMA Table Size : Ch#27 154#define MO_DMA28_CNT2 0x30015C // {11}RW* DMA Table Size : Ch#28 155#define MO_DMA29_CNT2 0x300160 // {11}RW* DMA Table Size : Ch#29 156#define MO_DMA30_CNT2 0x300164 // {11}RW* DMA Table Size : Ch#30 157#define MO_DMA31_CNT2 0x300168 // {11}RW* DMA Table Size : Ch#31 158#define MO_DMA32_CNT2 0x30016C // {11}RW* DMA Table Size : Ch#32 159 | 66 67#define MO_PDMA_STHRSH 0x200000 // Source threshold 68#define MO_PDMA_STADRS 0x200004 // Source target address 69#define MO_PDMA_SIADRS 0x200008 // Source internal address 70#define MO_PDMA_SCNTRL 0x20000C // Source control 71#define MO_PDMA_DTHRSH 0x200010 // Destination threshold 72#define MO_PDMA_DTADRS 0x200014 // Destination target address 73#define MO_PDMA_DIADRS 0x200018 // Destination internal address --- 76 unchanged lines hidden (view full) --- 150#define MO_DMA26_CNT2 0x300154 // {11}RW* DMA Table Size : Ch#26 151#define MO_DMA27_CNT2 0x300158 // {11}RW* DMA Table Size : Ch#27 152#define MO_DMA28_CNT2 0x30015C // {11}RW* DMA Table Size : Ch#28 153#define MO_DMA29_CNT2 0x300160 // {11}RW* DMA Table Size : Ch#29 154#define MO_DMA30_CNT2 0x300164 // {11}RW* DMA Table Size : Ch#30 155#define MO_DMA31_CNT2 0x300168 // {11}RW* DMA Table Size : Ch#31 156#define MO_DMA32_CNT2 0x30016C // {11}RW* DMA Table Size : Ch#32 157 |
| 158/* 159 * Video registers 160 */ |
|
| 160 | 161 |
| 161/* ---------------------------------------------------------------------- */ 162/* Video registers */ 163 | |
| 164#define MO_VIDY_DMA 0x310000 // {64}RWp Video Y 165#define MO_VIDU_DMA 0x310008 // {64}RWp Video U 166#define MO_VIDV_DMA 0x310010 // {64}RWp Video V 167#define MO_VBI_DMA 0x310018 // {64}RWp VBI (Vertical blanking interval) 168 169#define MO_DEVICE_STATUS 0x310100 170#define MO_INPUT_FORMAT 0x310104 171#define MO_AGC_BURST 0x31010c --- 40 unchanged lines hidden (view full) --- 212#define MO_VBI_GPCNT 0x31C02C // {16}RO VBI general purpose counter 213#define MO_VIDY_GPCNTRL 0x31C030 // {2}WO Video Y general purpose control 214#define MO_VIDU_GPCNTRL 0x31C034 // {2}WO Video U general purpose control 215#define MO_VIDV_GPCNTRL 0x31C038 // {2}WO Video V general purpose control 216#define MO_VBI_GPCNTRL 0x31C03C // {2}WO VBI general purpose counter 217#define MO_VID_DMACNTRL 0x31C040 // {8}RW Video DMA control 218#define MO_VID_XFR_STAT 0x31C044 // {1}RO Video transfer status 219 | 162#define MO_VIDY_DMA 0x310000 // {64}RWp Video Y 163#define MO_VIDU_DMA 0x310008 // {64}RWp Video U 164#define MO_VIDV_DMA 0x310010 // {64}RWp Video V 165#define MO_VBI_DMA 0x310018 // {64}RWp VBI (Vertical blanking interval) 166 167#define MO_DEVICE_STATUS 0x310100 168#define MO_INPUT_FORMAT 0x310104 169#define MO_AGC_BURST 0x31010c --- 40 unchanged lines hidden (view full) --- 210#define MO_VBI_GPCNT 0x31C02C // {16}RO VBI general purpose counter 211#define MO_VIDY_GPCNTRL 0x31C030 // {2}WO Video Y general purpose control 212#define MO_VIDU_GPCNTRL 0x31C034 // {2}WO Video U general purpose control 213#define MO_VIDV_GPCNTRL 0x31C038 // {2}WO Video V general purpose control 214#define MO_VBI_GPCNTRL 0x31C03C // {2}WO VBI general purpose counter 215#define MO_VID_DMACNTRL 0x31C040 // {8}RW Video DMA control 216#define MO_VID_XFR_STAT 0x31C044 // {1}RO Video transfer status 217 |
| 218/* 219 * audio registers 220 */ |
|
| 220 | 221 |
| 221/* ---------------------------------------------------------------------- */ 222/* audio registers */ 223 | |
| 224#define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream 225#define MO_AUDU_DMA 0x320008 // {64}RWp Audio upstream 226#define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream) 227#define MO_AUDD_GPCNT 0x32C020 // {16}RO Audio down general purpose counter 228#define MO_AUDU_GPCNT 0x32C024 // {16}RO Audio up general purpose counter 229#define MO_AUDR_GPCNT 0x32C028 // {16}RO Audio RDS general purpose counter 230#define MO_AUDD_GPCNTRL 0x32C030 // {2}WO Audio down general purpose control 231#define MO_AUDU_GPCNTRL 0x32C034 // {2}WO Audio up general purpose control --- 200 unchanged lines hidden (view full) --- 432// Audio QAM Register Addresses 433#define AUD_PDF_DDS_CNST_BYTE2 0x320d01 434#define AUD_PDF_DDS_CNST_BYTE1 0x320d02 435#define AUD_PDF_DDS_CNST_BYTE0 0x320d03 436#define AUD_PHACC_FREQ_8MSB 0x320d2a 437#define AUD_PHACC_FREQ_8LSB 0x320d2b 438#define AUD_QAM_MODE 0x320d04 439 | 222#define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream 223#define MO_AUDU_DMA 0x320008 // {64}RWp Audio upstream 224#define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream) 225#define MO_AUDD_GPCNT 0x32C020 // {16}RO Audio down general purpose counter 226#define MO_AUDU_GPCNT 0x32C024 // {16}RO Audio up general purpose counter 227#define MO_AUDR_GPCNT 0x32C028 // {16}RO Audio RDS general purpose counter 228#define MO_AUDD_GPCNTRL 0x32C030 // {2}WO Audio down general purpose control 229#define MO_AUDU_GPCNTRL 0x32C034 // {2}WO Audio up general purpose control --- 200 unchanged lines hidden (view full) --- 430// Audio QAM Register Addresses 431#define AUD_PDF_DDS_CNST_BYTE2 0x320d01 432#define AUD_PDF_DDS_CNST_BYTE1 0x320d02 433#define AUD_PDF_DDS_CNST_BYTE0 0x320d03 434#define AUD_PHACC_FREQ_8MSB 0x320d2a 435#define AUD_PHACC_FREQ_8LSB 0x320d2b 436#define AUD_QAM_MODE 0x320d04 437 |
| 438/* 439 * transport stream registers 440 */ |
|
| 440 | 441 |
| 441/* ---------------------------------------------------------------------- */ 442/* transport stream registers */ 443 | |
| 444#define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream 445#define MO_TS_GPCNT 0x33C020 // {16}RO TS general purpose counter 446#define MO_TS_GPCNTRL 0x33C030 // {2}WO TS general purpose control 447#define MO_TS_DMACNTRL 0x33C040 // {6}RW TS DMA control 448#define MO_TS_XFR_STAT 0x33C044 // {1}RO TS transfer status 449#define MO_TS_LNGTH 0x33C048 // {12}RW TS line length 450 451#define TS_HW_SOP_CNTRL 0x33C04C 452#define TS_GEN_CNTRL 0x33C050 453#define TS_BD_PKT_STAT 0x33C054 454#define TS_SOP_STAT 0x33C058 455#define TS_FIFO_OVFL_STAT 0x33C05C 456#define TS_VALERR_CNTRL 0x33C060 457 | 442#define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream 443#define MO_TS_GPCNT 0x33C020 // {16}RO TS general purpose counter 444#define MO_TS_GPCNTRL 0x33C030 // {2}WO TS general purpose control 445#define MO_TS_DMACNTRL 0x33C040 // {6}RW TS DMA control 446#define MO_TS_XFR_STAT 0x33C044 // {1}RO TS transfer status 447#define MO_TS_LNGTH 0x33C048 // {12}RW TS line length 448 449#define TS_HW_SOP_CNTRL 0x33C04C 450#define TS_GEN_CNTRL 0x33C050 451#define TS_BD_PKT_STAT 0x33C054 452#define TS_SOP_STAT 0x33C058 453#define TS_FIFO_OVFL_STAT 0x33C05C 454#define TS_VALERR_CNTRL 0x33C060 455 |
| 456/* 457 * VIP registers 458 */ |
|
| 458 | 459 |
| 459/* ---------------------------------------------------------------------- */ 460/* VIP registers */ 461 | |
| 462#define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream 463#define MO_VIPU_DMA 0x340008 // {64}RWp VIP upstream 464#define MO_VIPD_GPCNT 0x34C020 // {16}RO VIP down general purpose counter 465#define MO_VIPU_GPCNT 0x34C024 // {16}RO VIP up general purpose counter 466#define MO_VIPD_GPCNTRL 0x34C030 // {2}WO VIP down general purpose control 467#define MO_VIPU_GPCNTRL 0x34C034 // {2}WO VIP up general purpose control 468#define MO_VIP_DMACNTRL 0x34C040 // {6}RW VIP DMA control 469#define MO_VIP_XFR_STAT 0x34C044 // {1}RO VIP transfer status 470#define MO_VIP_CFG 0x340048 // VIP configuration 471#define MO_VIPU_CNTRL 0x34004C // VIP upstream control #1 472#define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2 473#define MO_VIPD_LNGTH 0x340054 // VIP downstream line length 474#define MO_VIP_BRSTLN 0x340058 // VIP burst length 475#define MO_VIP_INTCNTRL 0x34C05C // VIP Interrupt Control 476#define MO_VIP_XFTERM 0x340060 // VIP transfer terminate 477 | 460#define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream 461#define MO_VIPU_DMA 0x340008 // {64}RWp VIP upstream 462#define MO_VIPD_GPCNT 0x34C020 // {16}RO VIP down general purpose counter 463#define MO_VIPU_GPCNT 0x34C024 // {16}RO VIP up general purpose counter 464#define MO_VIPD_GPCNTRL 0x34C030 // {2}WO VIP down general purpose control 465#define MO_VIPU_GPCNTRL 0x34C034 // {2}WO VIP up general purpose control 466#define MO_VIP_DMACNTRL 0x34C040 // {6}RW VIP DMA control 467#define MO_VIP_XFR_STAT 0x34C044 // {1}RO VIP transfer status 468#define MO_VIP_CFG 0x340048 // VIP configuration 469#define MO_VIPU_CNTRL 0x34004C // VIP upstream control #1 470#define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2 471#define MO_VIPD_LNGTH 0x340054 // VIP downstream line length 472#define MO_VIP_BRSTLN 0x340058 // VIP burst length 473#define MO_VIP_INTCNTRL 0x34C05C // VIP Interrupt Control 474#define MO_VIP_XFTERM 0x340060 // VIP transfer terminate 475 |
| 476/* 477 * misc registers 478 */ |
|
| 478 | 479 |
| 479/* ---------------------------------------------------------------------- */ 480/* misc registers */ 481 | |
| 482#define MO_M2M_DMA 0x350000 // {64}RWp Mem2Mem DMA Bfr 483#define MO_GP0_IO 0x350010 // {32}RW* GPIOoutput enablesdata I/O 484#define MO_GP1_IO 0x350014 // {32}RW* GPIOoutput enablesdata I/O 485#define MO_GP2_IO 0x350018 // {32}RW* GPIOoutput enablesdata I/O 486#define MO_GP3_IO 0x35001C // {32}RW* GPIO Mode/Ctrloutput enables 487#define MO_GPIO 0x350020 // {32}RW* GPIO I2C Ctrldata I/O 488#define MO_GPOE 0x350024 // {32}RW GPIO I2C Ctrloutput enables 489#define MO_GP_ISM 0x350028 // {16}WO GPIO Intr Sens/Pol --- 14 unchanged lines hidden (view full) --- 504#define MO_DDSCFG_IO 0x35C054 // DDS Configuration reg 505#define MO_SAMPLE_IO 0x35C058 // IRIn sample reg 506#define MO_SRST_IO 0x35C05C // Output system reset reg 507 508#define MO_INT1_MSK 0x35C060 // DMA RISC interrupt mask 509#define MO_INT1_STAT 0x35C064 // DMA RISC interrupt status 510#define MO_INT1_MSTAT 0x35C068 // DMA RISC interrupt masked status 511 | 480#define MO_M2M_DMA 0x350000 // {64}RWp Mem2Mem DMA Bfr 481#define MO_GP0_IO 0x350010 // {32}RW* GPIOoutput enablesdata I/O 482#define MO_GP1_IO 0x350014 // {32}RW* GPIOoutput enablesdata I/O 483#define MO_GP2_IO 0x350018 // {32}RW* GPIOoutput enablesdata I/O 484#define MO_GP3_IO 0x35001C // {32}RW* GPIO Mode/Ctrloutput enables 485#define MO_GPIO 0x350020 // {32}RW* GPIO I2C Ctrldata I/O 486#define MO_GPOE 0x350024 // {32}RW GPIO I2C Ctrloutput enables 487#define MO_GP_ISM 0x350028 // {16}WO GPIO Intr Sens/Pol --- 14 unchanged lines hidden (view full) --- 502#define MO_DDSCFG_IO 0x35C054 // DDS Configuration reg 503#define MO_SAMPLE_IO 0x35C058 // IRIn sample reg 504#define MO_SRST_IO 0x35C05C // Output system reset reg 505 506#define MO_INT1_MSK 0x35C060 // DMA RISC interrupt mask 507#define MO_INT1_STAT 0x35C064 // DMA RISC interrupt status 508#define MO_INT1_MSTAT 0x35C068 // DMA RISC interrupt masked status 509 |
| 510/* 511 * i2c bus registers 512 */ |
|
| 512 | 513 |
| 513/* ---------------------------------------------------------------------- */ 514/* i2c bus registers */ 515 | |
| 516#define MO_I2C 0x368000 // I2C data/control 517#define MO_I2C_DIV (0xf<<4) 518#define MO_I2C_SYNC (1<<3) 519#define MO_I2C_W3B (1<<2) 520#define MO_I2C_SCL (1<<1) 521#define MO_I2C_SDA (1<<0) 522 523 | 514#define MO_I2C 0x368000 // I2C data/control 515#define MO_I2C_DIV (0xf<<4) 516#define MO_I2C_SYNC (1<<3) 517#define MO_I2C_W3B (1<<2) 518#define MO_I2C_SCL (1<<1) 519#define MO_I2C_SDA (1<<0) 520 521 |
| 524/* ---------------------------------------------------------------------- */ 525/* general purpose host registers */ 526/* FIXME: tyops? s/0x35/0x38/ ?? */ | 522/* 523 * general purpose host registers 524 * 525 * FIXME: tyops? s/0x35/0x38/ ?? 526 */ |
| 527 528#define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream 529#define MO_GPHSTU_DMA 0x350008 // {64}RWp Host upstream 530#define MO_GPHSTU_CNTRL 0x380048 // Host upstream control #1 531#define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2 532#define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length 533#define MO_GPHST_WSC 0x380054 // Host wait state control 534#define MO_GPHST_XFR 0x380058 // Host transfer control --- 5 unchanged lines hidden (view full) --- 540#define MO_GPHSTD_GPCNT 0x35C020 // Host down general purpose counter 541#define MO_GPHSTU_GPCNT 0x35C024 // Host up general purpose counter 542#define MO_GPHSTD_GPCNTRL 0x38C030 // Host down general purpose control 543#define MO_GPHSTU_GPCNTRL 0x38C034 // Host up general purpose control 544#define MO_GPHST_DMACNTRL 0x38C040 // Host DMA control 545#define MO_GPHST_XFR_STAT 0x38C044 // Host transfer status 546#define MO_GPHST_SOFT_RST 0x38C06C // Host software reset 547 | 527 528#define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream 529#define MO_GPHSTU_DMA 0x350008 // {64}RWp Host upstream 530#define MO_GPHSTU_CNTRL 0x380048 // Host upstream control #1 531#define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2 532#define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length 533#define MO_GPHST_WSC 0x380054 // Host wait state control 534#define MO_GPHST_XFR 0x380058 // Host transfer control --- 5 unchanged lines hidden (view full) --- 540#define MO_GPHSTD_GPCNT 0x35C020 // Host down general purpose counter 541#define MO_GPHSTU_GPCNT 0x35C024 // Host up general purpose counter 542#define MO_GPHSTD_GPCNTRL 0x38C030 // Host down general purpose control 543#define MO_GPHSTU_GPCNTRL 0x38C034 // Host up general purpose control 544#define MO_GPHST_DMACNTRL 0x38C040 // Host DMA control 545#define MO_GPHST_XFR_STAT 0x38C044 // Host transfer status 546#define MO_GPHST_SOFT_RST 0x38C06C // Host software reset 547 |
| 548/* 549 * RISC instructions 550 */ |
|
| 548 | 551 |
| 549/* ---------------------------------------------------------------------- */ 550/* RISC instructions */ 551 | |
| 552#define RISC_SYNC 0x80000000 553#define RISC_SYNC_ODD 0x80000000 554#define RISC_SYNC_EVEN 0x80000200 555#define RISC_RESYNC 0x80008000 556#define RISC_RESYNC_ODD 0x80008000 557#define RISC_RESYNC_EVEN 0x80008200 558#define RISC_WRITE 0x10000000 559#define RISC_WRITEC 0x50000000 --- 13 unchanged lines hidden (view full) --- 573#define RISC_IRQ1 0x01000000 574 575#define RISC_CNT_NONE 0x00000000 576#define RISC_CNT_INC 0x00010000 577#define RISC_CNT_RSVR 0x00020000 578#define RISC_CNT_RESET 0x00030000 579#define RISC_JMP_SRP 0x01 580 | 552#define RISC_SYNC 0x80000000 553#define RISC_SYNC_ODD 0x80000000 554#define RISC_SYNC_EVEN 0x80000200 555#define RISC_RESYNC 0x80008000 556#define RISC_RESYNC_ODD 0x80008000 557#define RISC_RESYNC_EVEN 0x80008200 558#define RISC_WRITE 0x10000000 559#define RISC_WRITEC 0x50000000 --- 13 unchanged lines hidden (view full) --- 573#define RISC_IRQ1 0x01000000 574 575#define RISC_CNT_NONE 0x00000000 576#define RISC_CNT_INC 0x00010000 577#define RISC_CNT_RSVR 0x00020000 578#define RISC_CNT_RESET 0x00030000 579#define RISC_JMP_SRP 0x01 580 |
| 581/* 582 * various constants 583 */ |
|
| 581 | 584 |
| 582/* ---------------------------------------------------------------------- */ 583/* various constants */ 584 | |
| 585// DMA 586/* Interrupt mask/status */ 587#define PCI_INT_VIDINT (1 << 0) 588#define PCI_INT_AUDINT (1 << 1) 589#define PCI_INT_TSINT (1 << 2) 590#define PCI_INT_VIPINT (1 << 3) 591#define PCI_INT_HSTINT (1 << 4) 592#define PCI_INT_TM1INT (1 << 5) --- 233 unchanged lines hidden --- | 585// DMA 586/* Interrupt mask/status */ 587#define PCI_INT_VIDINT (1 << 0) 588#define PCI_INT_AUDINT (1 << 1) 589#define PCI_INT_TSINT (1 << 2) 590#define PCI_INT_VIPINT (1 << 3) 591#define PCI_INT_HSTINT (1 << 4) 592#define PCI_INT_TM1INT (1 << 5) --- 233 unchanged lines hidden --- |