| leds-ss4200.c (d3b6492afada275d2e33b81a8a3737c9cb0016a4) | leds-ss4200.c (98ea1ea20cb7090d5ae2003c23fc8a7f14fca4c7) |
|---|---|
| 1/* 2 * SS4200-E Hardware API 3 * Copyright (c) 2009, Intel Corporation. 4 * Copyright IBM Corporation, 2009 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. --- 249 unchanged lines hidden (view full) --- 258} 259 260 261/* 262 * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have 263 * already taken care of this, but we will do so in a non destructive manner 264 * so that we have what we need whether the BIOS did it or not. 265 */ | 1/* 2 * SS4200-E Hardware API 3 * Copyright (c) 2009, Intel Corporation. 4 * Copyright IBM Corporation, 2009 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. --- 249 unchanged lines hidden (view full) --- 258} 259 260 261/* 262 * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have 263 * already taken care of this, but we will do so in a non destructive manner 264 * so that we have what we need whether the BIOS did it or not. 265 */ |
| 266static int __devinit ich7_gpio_init(struct device *dev) | 266static int ich7_gpio_init(struct device *dev) |
| 267{ 268 int i; 269 u32 config_data = 0; 270 u32 all_nas_led = 0; 271 272 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) 273 all_nas_led |= (1<<nasgpio_leds[i].gpio_bit); 274 --- 62 unchanged lines hidden (view full) --- 337 } 338} 339 340/* 341 * The OS has determined that the LPC of the Intel ICH7 Southbridge is present 342 * so we can retrive the required operational information and prepare the GPIO. 343 */ 344static struct pci_dev *nas_gpio_pci_dev; | 267{ 268 int i; 269 u32 config_data = 0; 270 u32 all_nas_led = 0; 271 272 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) 273 all_nas_led |= (1<<nasgpio_leds[i].gpio_bit); 274 --- 62 unchanged lines hidden (view full) --- 337 } 338} 339 340/* 341 * The OS has determined that the LPC of the Intel ICH7 Southbridge is present 342 * so we can retrive the required operational information and prepare the GPIO. 343 */ 344static struct pci_dev *nas_gpio_pci_dev; |
| 345static int __devinit ich7_lpc_probe(struct pci_dev *dev, | 345static int ich7_lpc_probe(struct pci_dev *dev, |
| 346 const struct pci_device_id *id) 347{ 348 int status; 349 u32 gc = 0; 350 351 status = pci_enable_device(dev); 352 if (status) { 353 dev_err(&dev->dev, "pci_enable_device failed\n"); --- 100 unchanged lines hidden (view full) --- 454static ssize_t nas_led_blink_store(struct device *dev, 455 struct device_attribute *attr, 456 const char *buf, size_t size) 457{ 458 int ret; 459 struct led_classdev *led = dev_get_drvdata(dev); 460 unsigned long blink_state; 461 | 346 const struct pci_device_id *id) 347{ 348 int status; 349 u32 gc = 0; 350 351 status = pci_enable_device(dev); 352 if (status) { 353 dev_err(&dev->dev, "pci_enable_device failed\n"); --- 100 unchanged lines hidden (view full) --- 454static ssize_t nas_led_blink_store(struct device *dev, 455 struct device_attribute *attr, 456 const char *buf, size_t size) 457{ 458 int ret; 459 struct led_classdev *led = dev_get_drvdata(dev); 460 unsigned long blink_state; 461 |
| 462 ret = kstrtoul(buf, 10, &blink_state); | 462 ret = strict_strtoul(buf, 10, &blink_state); |
| 463 if (ret) 464 return ret; 465 466 nasgpio_led_set_attr(led, GPO_BLINK, blink_state); 467 468 return size; 469} 470 --- 87 unchanged lines hidden --- | 463 if (ret) 464 return ret; 465 466 nasgpio_led_set_attr(led, GPO_BLINK, blink_state); 467 468 return size; 469} 470 --- 87 unchanged lines hidden --- |